Ð þíLþHH4(ÊGìsamtec VIN|ING FPGA#!altr,socfpga-cyclone5altr,socfpgachosen,console=ttyS0,115200aliases5/soc/ethernet@ff702000?/soc/ethernet@ff702000I/soc/serial0@ffc02000Q/soc/serial1@ffc03000Y/soc/timer0@ffc08000`/soc/timer1@ffc09000g/soc/timer2@ffd00000n/soc/timer3@ffd01000memoryumemory�@cpus…altr,socfpga-smpcpu@0!arm,cortex-a9ucpu�“cpu@1!arm,cortex-a9ucpu�“intc@fffed000!arm,cortex-a9-gic¤µ�ÿþÐÿþÁÊÐsoc !simple-bususocØéamba !simple-busépdma@ffe01000!arm,pl330arm,primecell�ÿà`ðhijklmnoû " )apb_pclkÊ+Ð+can@ffc00000 !bosch,d_can�ÿÀ0ðƒ„…†" 5disabledcan@ffc01000 !bosch,d_can�ÿÀ0ð‡ˆ‰Š" 5disabledclkmgr@ffd04000 !altr,clk-mgr�ÿÐ@clocksosc1< !fixed-clockI}x@ÊÐosc2< !fixed-clockÊÐf2s_periph_ref_clk< !fixed-clockÊ Ð f2s_sdram_ref_clk< !fixed-clockÊ Ð main_pll<!altr,socfpga-pll-clock"�@ÊÐmpuclk<!altr,socfpga-perip-clk" Yà �HÊ Ð mainclk<!altr,socfpga-perip-clk" Yä �LÊÐdbg_base_clk<!altr,socfpga-perip-clk" Yè �PÊÐmain_qspi_clk<!altr,socfpga-perip-clk"�TÊÐmain_nand_sdmmc_clk<!altr,socfpga-perip-clk"�XÊÐcfg_h2f_usr0_clk<!altr,socfpga-perip-clk"�\ÊÐperiph_pll<!altr,socfpga-pll-clock " �€Ê Ð emac0_clk<!altr,socfpga-perip-clk" �ˆÊÐemac1_clk<!altr,socfpga-perip-clk" �ŒÊÐper_qsi_clk<!altr,socfpga-perip-clk" ��ÊÐper_nand_mmc_clk<!altr,socfpga-perip-clk" �”ÊÐper_base_clk<!altr,socfpga-perip-clk" �˜ÊÐh2f_usr1_clk<!altr,socfpga-perip-clk" �œÊÐsdram_pll<!altr,socfpga-pll-clock " �ÀÊ Ð ddr_dqs_clk<!altr,socfpga-perip-clk" �ÈÊÐddr_2x_dqs_clk<!altr,socfpga-perip-clk" �ÌÊÐddr_dq_clk<!altr,socfpga-perip-clk" �ÐÊÐh2f_usr2_clk<!altr,socfpga-perip-clk" �ÔÊÐmpu_periph_clk<!altr,socfpga-perip-clk" aÊ*Ð*mpu_l2_ram_clk<!altr,socfpga-perip-clk" al4_main_clk<!altr,socfpga-gate-clk"o`ÊÐl3_main_clk<!altr,socfpga-perip-clk"al3_mp_clk<!altr,socfpga-gate-clk" Ydo`ÊÐl3_sp_clk<!altr,socfpga-gate-clk" Ydl4_mp_clk<!altr,socfpga-gate-clk" Ydo`Ê$Ð$l4_sp_clk<!altr,socfpga-gate-clk" Ydo`Ê%Ð%dbg_at_clk<!altr,socfpga-gate-clk" Yho`ÊÐdbg_clk<!altr,socfpga-gate-clk" Yho`dbg_trace_clk<!altr,socfpga-gate-clk" Ylo`dbg_timer_clk<!altr,socfpga-gate-clk"o`cfg_clk<!altr,socfpga-gate-clk"o`h2f_user0_clk<!altr,socfpga-gate-clk"o` emac_0_clk<!altr,socfpga-gate-clk"o emac_1_clk<!altr,socfpga-gate-clk"o usb_mp_clk<!altr,socfpga-gate-clk"o  Y¤Ê,Ð,spi_m_clk<!altr,socfpga-gate-clk"o  Y¤Ê)Ð)can0_clk<!altr,socfpga-gate-clk"o  Y¤ÊÐcan1_clk<!altr,socfpga-gate-clk"o  Y¤ ÊÐgpio_db_clk<!altr,socfpga-gate-clk"o  Y¨h2f_user1_clk<!altr,socfpga-gate-clk"o sdmmc_clk<!altr,socfpga-gate-clk " o x‡ÊÐsdmmc_clk_divided<!altr,socfpga-gate-clk"o aÊ'Ð'nand_x_clk<!altr,socfpga-gate-clk " o  nand_clk<!altr,socfpga-gate-clk " o  aqspi_clk<!altr,socfpga-gate-clk " o  ddr_dqs_clk_gate<!altr,socfpga-gate-clk"oØddr_2x_dqs_clk_gate<!altr,socfpga-gate-clk"oØddr_dq_clk_gate<!altr,socfpga-gate-clk"oØh2f_user2_clk<!altr,socfpga-gate-clk"oØfpgamgr@ff706000!altr,socfpga-fpga-mgr�ÿp`ÿ¹ ð¯ethernet@ff7000000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac ‚ `�ÿp  ðs•macirq¥" )stmmaceth±!  ¸stmmacethÄ߀û  5disabledethernet@ff7020000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac ‚ `�ÿp  ðx•macirq¥" )stmmaceth±!! ¸stmmacethÄ߀û 5okayrgmii " +#; Q'''mdio0!snps,dwmac-mdioethernet-phy@1�fs€�š§ (³ÀÐÊ"Ð"gpio@ff708000!snps,dw-apb-gpio�ÿp€"$5okaygpio-controller@0!snps,dw-apb-gpio-portÌÜè�µ¤ ð¤Ê#Ð#gpio@ff709000!snps,dw-apb-gpio�ÿp�"$5okaygpio-controller@0!snps,dw-apb-gpio-portÌÜè�µ¤ ð¥Ê.Ð.gpio@ff70a000!snps,dw-apb-gpio�ÿp "$5okaygpio-controller@0!snps,dw-apb-gpio-portÌÜè�µ¤ ð¦Ê/Ð/i2c@ffc04000!snps,designware-i2c�ÿÀ@"% ðž5okaypca9557@1f !nxp,pca9557�ÌÜlm75@48!lm75�Hat24@50 !at24,24c01ö�Pi2cswitch@70 !nxp,pca9548�pi2c@0�eeprom@51 !at,24c01ö�Qi2c@1�eeprom@51 !at,24c01ö�Qi2c@2�eeprom@51 !at,24c01ö�Qi2c@3�eeprom@51 !at,24c01ö�Qi2c@4�eeprom@51 !at,24c01ö�Qi2c@5�eeprom@51 !at,24c01ö�Qi2c@6�eeprom@51 !at,24c01ö�Qi2c@7�eeprom@51 !at,24c01ö�Qi2c@ffc05000!snps,designware-i2c�ÿÀP"% ðŸ5okayI† at24@50 !at24,24c02ö�Pi2c@ffc06000!snps,designware-i2c�ÿÀ`"% ð  5disabledi2c@ffc07000!snps,designware-i2c�ÿÀp"% ð¡ 5disabledeccmgr@ffd08140!altr,socfpga-ecc-managerél2-ecc@ffd08140!altr,socfpga-l2-ecc�ÿÐ�@ð$%ocram-ecc@ffd08144!altr,socfpga-ocram-ecc�ÿÐ�Dÿ&ð²³l2-cache@fffef000!arm,pl310-cache�ÿþð ð&  .?MÊÐdwmmc0@ff704000!altr,socfpga-dw-mshc�ÿp@ ð‹þ"$')biuciu 5disabled\fpzŒsram@ffff0000 !mmio-sram�ÿÿÊ&Ð&rstmgr@ffd05000� !altr,rst-mgr�ÿÐPªÊ!Ð!snoop-control-unit@fffec000!arm,cortex-a9-scu�ÿþÀsdr@ffc25000!syscon�ÿÂPÊ(Ð(sdramedac!altr,sdram-edac½( ð'spi@fff00000!snps,dw-apb-ssi�ÿð ðšÍ") 5disabledspi@fff01000!snps,dw-apb-ssi�ÿð ð›Í") 5disabledsysmgr@ffd08000!altr,sys-mgrsyscon�ÿЀ@ÔÿЀÄÊ Ð timer@fffec600!arm,cortex-a9-twd-timer�ÿþÆ ð "*timer0@ffc08000!snps,dw-apb-timer ð§�ÿÀ€"%)timertimer1@ffc09000!snps,dw-apb-timer ð¨�ÿÀ�"%)timertimer2@ffd00000!snps,dw-apb-timer ð©�ÿÐ")timertimer3@ffd01000!snps,dw-apb-timer ðª�ÿÐ")timerserial0@ffc02000!snps,dw-apb-uart�ÿÀ  ð¢äî"%û++txrxserial1@ffc03000!snps,dw-apb-uart�ÿÀ0 ð£äî"%û++txrxusbphy@0 !usb-nop-xceiv5okayÊ-Ð-usb@ffb00000 !snps,dwc2�ÿ°ÿÿ ð}",)otg±!"¸dwc2- usb2-phy5okay$hostusb@ffb40000 !snps,dwc2�ÿ´ÿÿ ð€",)otg±!#¸dwc2- usb2-phy5okay $peripheralwatchdog@ffd02000 !snps,dw-wdt�ÿÐ  ð«"5okaywatchdog@ffd03000 !snps,dw-wdt�ÿÐ0 ð¬" 5disabledleds !gpio-ledshps_led0,hps:green:led0 ð. 2heartbeathps_led1 ,hps:red:led0 ð.2nonehps_led2,hps:green:led1 ð. 2heartbeathps_led3 ,hps:red:led1 ð/2nonegpio-keys !gpio-keyshps_temp0,BTN_0 ð/Hhps_hkey0,BTN_1 ð/Hhps_hkey1 ,hps_hkey1 ð/Htregulator-usb-nrst!regulator-fixed Susb_nrstbLK@zLK@ 6.’p£¶ #address-cells#size-cellsmodelcompatiblebootargsethernet0ethernet1serial0serial1timer0timer1timer2timer3device_typeregenable-methodnext-level-cache#interrupt-cellsinterrupt-controllerlinux,phandleinterrupt-parentrangesinterrupts#dma-cells#dma-channels#dma-requestsclocksclock-namesstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phasealtr,sysmgr-sysconinterrupt-namesmac-addressresetsreset-namessnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthphy-modephy-handlesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-psgpio-controller#gpio-cellssnps,nr-gpiospagesizeiramcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrnum-slotsbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeed#reset-cellsaltr,modrst-offsetaltr,sdr-sysconnum-cscpu1-start-addrreg-shiftreg-io-widthdmasdma-names#phy-cellsphysphy-namesdr_modelabellinux,default-triggerlinux,coderegulator-nameregulator-min-microvoltregulator-max-microvoltstartup-delay-usenable-active-highregulator-always-on