Ð þí‹S8‚8( ‚google,veyron-mickey-rev8google,veyron-mickey-rev7google,veyron-mickey-rev6google,veyron-mickey-rev5google,veyron-mickey-rev4google,veyron-mickey-rev3google,veyron-mickey-rev2google,veyron-mickey-rev1google,veyron-mickey-rev0google,veyron-mickeygoogle,veyronrockchip,rk3288&7Google Mickeychosenaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000…/serial@ff190000�/serial@ff690000•/serial@ff1b0000�/serial@ff1c0000¥/spi@ff110000ª/spi@ff120000¯/spi@ff130000memory´memoryÀ€arm-pmuarm,cortex-a12-pmu0Ä—˜™šÏcpusârockchip,rk3066-smpðcpu@500´cpuarm,cortex-a12Àýhw@\À@™p‰@Ö @Л@O€O€Èàa€� s€B@ žÀ~ð 'À » 9À » KÀ » ì0 » $œ@29EKcpu@501´cpuarm,cortex-a12ÀýEKcpu@502´cpuarm,cortex-a12ÀýEKcpu@503´cpuarm,cortex-a12ÀýEKamba simple-busSdma-controller@ff250000arm,pl330arm,primecellÀÿ%@ÄZe2 €apb_pclkEKdma-controller@ff600000arm,pl330arm,primecellÀÿ`@ÄZe2Á €apb_pclk Œdisableddma-controller@ffb20000arm,pl330arm,primecellÀÿ²@ÄZe2Á €apb_pclkEHKHreserved-memorySdma-unusable@fe000000Àþoscillator fixed-clock“n6£xin24m¶E K timerarm,armv7-timerÃ0Ä   “n6timer@ff810000rockchip,rk3288-timerÀÿ�  ÄH 2 a €timerpclkdisplay-subsystemrockchip,display-subsystemç dwmmc@ff0c0000rockchip,rk3288-dw-mshcí€ðÑ€ 2ÈDrv€biuciuciu-driveciu-sample Ä Àÿ @ Œdisableddwmmc@ff0d0000rockchip,rk3288-dw-mshcí€ðÑ€ 2ÉEsw€biuciuciu-driveciu-sample Ä!Àÿ @Œokay &3I Tbldefault z „‘ž«¹Ådwmmc@ff0e0000rockchip,rk3288-dw-mshcí€ðÑ€ 2ÊFtx€biuciuciu-driveciu-sample Ä"Àÿ@ Œdisableddwmmc@ff0f0000rockchip,rk3288-dw-mshcí€ðÑ€ 2ËGuy€biuciuciu-driveciu-sample Ä#Àÿ@Œokay ÒäžITbldefault zsaradc@ff100000rockchip,saradcÀÿ Ä$ 2I[€saradcapb_pclkýW saradc-apb Œdisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi2AR€spiclkapb_pclk+  0txrx Ä,ldefaultzÀÿ Œdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi2BS€spiclkapb_pclk+ 0txrx Ä-ldefaultzÀÿ Œdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi2CT€spiclkapb_pclk+0txrx Ä.ldefaultz !"ÀÿŒokay: flash@0jedec,spi-norMúð€Ài2c@ff140000rockchip,rk3288-i2cÀÿ Ä>€i2c2Mldefaultz#Œokay“€_2wdtpm@20infineon,slb9645ttÀ Ži2c@ff150000rockchip,rk3288-i2cÀÿ Ä?€i2c2Oldefaultz$ Œdisabledi2c@ff160000rockchip,rk3288-i2cÀÿ Ä@€i2c2Pldefaultz% Œdisabled“€_2w,i2c@ff170000rockchip,rk3288-i2cÀÿ ÄA€i2c2Qldefaultz&Œokay“† _,wèEYKYserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uartÀÿ Ä7¦°2MU€baudclkapb_pclkldefault z'()Œokay½MÍÜlserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uartÀÿ Ä8¦°2NV€baudclkapb_pclkldefaultz*Œokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uartÀÿi Ä9¦°2OW€baudclkapb_pclkldefaultz+Œokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uartÀÿ Ä:¦°2PX€baudclkapb_pclkldefaultz, Œdisabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uartÀÿ Ä;¦°2QY€baudclkapb_pclkldefaultz- Œdisabledthermal-zonesreserve_thermalâèøˆ.cpu_thermalâdøˆ.tripscpu_crit_�"Ð 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Sÿp€smp-sram@0rockchip,rk3066-smp-sramÀsram@ff720000#rockchip,rk3288-pmu-srammmio-sramÀÿrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdÀÿsEKpower-controller!rockchip,rk3288-power-controllerÛ½h8 EKKKpd_vio@9À È2ÊÍÈÌÅÆ¾¿ÔÕÖÙÑÒchgfdehilkjpd_hevc@11À 2Ïoppd_video@12À 2ÐÜpd_gpu@13À 2Àreboot-modesyscon-reboot-modeï”öRBÃRBÃRBà  RBÃsyscon@ff740000rockchip,rk3288-sgrfsysconÀÿtclock-controller@ff760000rockchip,rk3288-cruÀÿvÄ7¶,H½ÑÝjÒÞk$Í#g¸€ׄÍeá£ðÑ€xhÀá£ðÑ€xhÀEKsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdÀÿwE7K7edp-phyrockchip,rk3288-dp-phy2h€24m9 ŒdisabledEVKVio-domains"rockchip,rk3288-io-voltage-domainŒokayD@NYg@w@…G‘usbphyrockchip,rk3288-usb-phyŒokayusb-phy@3209À 2]€phyclk¶E:K:usb-phy@3349À42^€phyclk¶E8K8usb-phy@3489ÀH2_€phyclk¶E9K9watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdtÀÿ€2p ÄOŒokaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdifÀÿ‹� €hclkmclk2ÐT+H0tx Ä6ldefaultzIÄ7 Œdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2sÀÿ‰ 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EKefuse@ffb40000rockchip,rockchip-efuseÀÿ´ 2q €pclk_efusecpu_leakage@17Àpinctrlrockchip,rk3288-pinctrlÄ7ðSldefaultsleepz\A\gpio0@ff750000rockchip,gpio-bankÀÿu ÄQ2@GW!6E<K<gpio1@ff780000rockchip,gpio-bankÀÿx ÄR2AGW!6gpio2@ff790000rockchip,gpio-bankÀÿy ÄS2BGW!6EeKegpio3@ff7a0000rockchip,gpio-bankÀÿz ÄT2CGW!6gpio4@ff7b0000rockchip,gpio-bankÀÿ{ ÄU2DGW!6EiKigpio5@ff7c0000rockchip,gpio-bankÀÿ| ÄV2EGW!6gpio6@ff7d0000rockchip,gpio-bankÀÿ} ÄW2FGW!6gpio7@ff7e0000rockchip,gpio-bankÀÿ~ ÄX2GGW!6EAKAgpio8@ff7f0000rockchip,gpio-bankÀÿ ÄY2HGW!6hdmihdmi-ddc c]]power-hdmi-onc ]EkKkpcfg-pull-upqE^K^pcfg-pull-down~E_K_pcfg-pull-none�E]K]pcfg-pull-none-12ma�š EaKasleepglobal-pwroffc]E\K\ddrio-pwroffc]ddr0-retentionc^ddr1-retentionc^edpedp-hpdc _i2c0i2c0-xfer c]]E;K;i2c1i2c1-xfer c]]E#K#i2c2i2c2-xfer c ] ]EBKBi2c3i2c3-xfer c]]E$K$i2c4i2c4-xfer c]]E%K%i2c5i2c5-xfer c]]E&K&i2s0i2s0-bus`c]]]]]]EJKJsdmmcsdmmc-clkc]sdmmc-cmdc^sdmmc-cdc^sdmmc-bus1c^sdmmc-bus4@c^^^^sdio0sdio0-bus1c^sdio0-bus4@c````EKsdio0-cmdc`EKsdio0-clkc`E K sdio0-cdc^sdio0-wpc^sdio0-pwrc^sdio0-bkpwrc^sdio0-intc^wifienable-hc]EhKhbt-enable-lc]EgKgsdio1sdio1-bus1c^sdio1-bus4@c^^^^sdio1-cdc^sdio1-wpc^sdio1-bkpwrc^sdio1-intc^sdio1-cmdc^sdio1-clkc]sdio1-pwrc ^emmcemmc-clkc`EKemmc-cmdc`EKemmc-pwrc ^emmc-bus1c^emmc-bus4@c^^^^emmc-bus8€c````````EKemmc-resetc ]EdKdspi0spi0-clkc ^EKspi0-cs0c ^EKspi0-txc^EKspi0-rxc^EKspi0-cs1c^spi1spi1-clkc ^EKspi1-cs0c ^EKspi1-rxc^EKspi1-txc^EKspi2spi2-cs1c^spi2-clkc^EKspi2-cs0c^E"K"spi2-rxc^E!K!spi2-txc ^E K uart0uart0-xfer c^]E'K'uart0-ctsc^E(K(uart0-rtsc]E)K)uart1uart1-xfer c^ ]E*K*uart1-ctsc ^uart1-rtsc ]uart2uart2-xfer c^]E+K+uart3uart3-xfer c^]E,K,uart3-ctsc ^uart3-rtsc ]uart4uart4-xfer c ^ ]E-K-uart4-ctsc^uart4-rtsc]tsadcotp-gpioc ]E5K5otp-outc ]E6K6pwm0pwm0-pinc]ECKCpwm1pwm1-pinc]EDKDpwm2pwm2-pinc]EEKEpwm3pwm3-pinc]EFKFgmacrgmii-pinsðc]]]]aaaa]]] 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#address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsclock-freq-min-maxfifo-depthbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablenum-slotspinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wp#io-channel-cellsreset-namesdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphysphy-namesneeds-reset-on-resumedr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvddio-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cells#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpio