Ð þí2–8.@(V.!,Rockchip RK3229 Evaluation board$2rockchip,rk3229-evbrockchip,rk3229chosenaliases=/serial@11010000E/serial@11020000M/serial@11030000memoryUmemorya`@cpuscpu@f00Ucpu2arm,cortex-a7ael s€B@}Œœ@š¡§cpu@f01Ucpu2arm,cortex-a7ae¡§cpu@f02Ucpu2arm,cortex-a7ae¡§cpu@f03Ucpu2arm,cortex-a7ae¡§amba 2simple-bus¯pdma@110f00002arm,pl330arm,primecella@¶ÁšÂ Ìapb_pclk¡§arm-pmu2arm,cortex-a7-pmu0¶LMNOØtimer2arm,armv7-timerë0¶   n6oscillator 2fixed-clockn6xin24m2¡§i2s1@100b0000(2rockchip,rk3228-i2srockchip,rk3066-i2sa @ ¶Ìi2s_clki2s_hclkšQ»?DtxrxNdefault\ fdisabledi2s0@100c0000(2rockchip,rk3228-i2srockchip,rk3066-i2sa @ ¶Ìi2s_clki2s_hclkšPº?  Dtxrx fdisabledi2s2@100e0000(2rockchip,rk3228-i2srockchip,rk3066-i2sa@ ¶Ìi2s_clki2s_hclkšR¼?Dtxrx fdisabledsyscon@110000002syscona¡§serial@110100002snps,dw-apb-uarta ¶7n6šMUÌbaudclkapb_pclkNdefault \ mw fdisabledserial@110200002snps,dw-apb-uarta ¶8n6šNVÌbaudclkapb_pclkNdefault\ mw fdisabledserial@110300002snps,dw-apb-uarta ¶9n6šOWÌbaudclkapb_pclkNdefault\ mwfokayi2c@110500002rockchip,rk3228-i2ca ¶$Ìi2cšLNdefault\ fdisabledi2c@110600002rockchip,rk3228-i2ca ¶%Ìi2cšMNdefault\ fdisabledi2c@110700002rockchip,rk3228-i2ca ¶&Ìi2cšNNdefault\ fdisabledi2c@110800002rockchip,rk3228-i2ca ¶'Ìi2cšONdefault\ fdisabledpwm@110b00002rockchip,rk3288-pwma „š^ÌpwmNdefault\ fdisabledpwm@110b00102rockchip,rk3288-pwma „š^ÌpwmNdefault\ fdisabledpwm@110b00202rockchip,rk3288-pwma „š^ÌpwmNdefault\ fdisabledpwm@110b00302rockchip,rk3288-pwma 0„š^ÌpwmNdefault\ fdisabledtimer@110c00002rockchip,rk3288-timera  ¶+ ša Ìtimerpclkclock-controller@110e00002rockchip,rk3228-crua�2œ©¹#g¸€¡§thermal-zonescpu-thermalÎdäˆòtripscpu_alert0pÐ\passive¡§cpu_alert1$øÐ\passive¡§cpu_crit_�Ð \criticalcooling-mapsmap0 ÿÿÿÿmap1 ÿÿÿÿÿÿÿÿtsadc@111500002rockchip,rk3228-tsadca ¶:šHXÌtsadcapb_pclkeW -tsadc-apbNinitdefaultsleep\9CMcs fdisabled¡§dwmmc@300200002rockchip,rk3288-dw-mshca0@ ¶<4`z€<4` šËGuyÌbiuciuciu_drvciu_sample�—ž¬¶Ndefault \ fdisabledethernet@302000002rockchip,rk3228-gmaca0  ¶Ámacirq8š~�‚€ÔoMÌstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mace8 -stmmaceth�fokay©}~ Ñ }èinputõ!rgmiiNdefault\"  # /'B@D0Minterrupt-controller@32010000 2arm,gic-400Vk a22 2@ 2`  ¶ ¡§pinctrl2rockchip,rk3228-pinctrl�¯gpio0@111100002rockchip,gpio-banka ¶3š@|ŒVkgpio1@111200002rockchip,gpio-banka ¶4šA|ŒVkgpio2@111300002rockchip,gpio-banka ¶5šB|ŒVk¡#§#gpio3@111400002rockchip,gpio-banka ¶6šC|ŒVkpcfg-pull-up˜pcfg-pull-down¥pcfg-pull-none´¡$§$pcfg-pull-none-drv-12maÁ ¡%§%emmcemmc-clkÐ$¡§emmc-cmdÐ$¡§emmc-bus8€Ð$$$$$$$$¡§gmacrgmii-pinsðÐ$ $$%%%% % %$$$$ $$¡"§"rmii-pins Ð$ $$%% %$$$$phy-pins Ð$$i2c0i2c0-xfer Ð$$¡§i2c1i2c1-xfer Ð$$¡§i2c2i2c2-xfer Ð$$¡§i2c3i2c3-xfer Ð$$¡§i2s1i2s1-bus�Ð$ $ $ $ $$$$$¡§pwm0pwm0-pinÐ$¡§pwm1pwm1-pinÐ$¡§pwm2pwm2-pinÐ $¡§pwm3pwm3-pinÐ $¡§tsadcotp-gpioÐ$¡§otp-outÐ$¡§uart0uart0-xfer Ð$$¡ § uart0-ctsÐ$¡ § uart0-rtsÐ$¡ § uart1uart1-xfer Ð $ $¡ § uart1-ctsÐ$uart1-rtsÐ $uart2uart2-xfer Ð$$¡ § uart2-ctsÐ$uart2-rtsÐ$ext_gmac 2fixed-clocksY@ ext_gmac2¡ § vcc-phy-regulator2regulator-fixedÞñvcc_phyw@w@0D¡!§! #address-cells#size-cellsinterrupt-parentmodelcompatibleserial0serial1serial2device_typeregresetsoperating-points#cooling-cellsclock-latencyclockslinux,phandlerangesinterrupts#dma-cellsclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsdmasdma-namespinctrl-namespinctrl-0statusreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempclock-freq-min-maxbus-widthdefault-sample-phasenum-slotsfifo-depthinterrupt-namesassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsenable-active-highregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-on