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fixed-clockÉÆ]@8>virt_19200000_ck  fixed-clockÉ$ø8>virt_26000000_ck  fixed-clockÉŒº€8>virt_38_4m_ck  fixed-clockÉIð8>dpll4_ck@d00 ti,omap3-dpll-per-clock}y D 08>dpll4_m2_ck@d48 ti,divider-clock}Ù?y Hä8 > dpll4_m2x2_mul_ck fixed-factor-clock} û8!>!dpll4_m2x2_ck@d00 ti,gate-clock}!­y 8">"omap_96m_alwon_fck fixed-factor-clock}"û8)>)dpll3_ck@d00 ti,omap3-dpll-core-clock}y @ 08>dpll3_m3_ck@1140 ti,divider-clock}­Ùy@ä8#>#dpll3_m3x2_mul_ck fixed-factor-clock}#û8$>$dpll3_m3x2_ck@d00 ti,gate-clock}$­ y 8%>%emu_core_alwon_ck fixed-factor-clock}%û8b>bsys_altclk  fixed-clockÉ8.>.mcbsp_clks  fixed-clockÉ8>dpll3_m2_ck@d40 ti,divider-clock}­Ùy @ä8>core_ck fixed-factor-clock}û8&>&dpll1_fck@940 ti,divider-clock}&­Ùy @ä8'>'dpll1_ck@904 ti,omap3-dpll-clock}'y  $ @ 48>dpll1_x2_ck fixed-factor-clock}û8(>(dpll1_x2m2_ck@944 ti,divider-clock}(Ùy Dä8<><cm_96m_fck fixed-factor-clock})û8*>*omap_96m_fck@d40  ti,mux-clock}*­y @8E>Edpll4_m3_ck@e40 ti,divider-clock}­Ù y@ä8+>+dpll4_m3x2_mul_ck fixed-factor-clock}+û8,>,dpll4_m3x2_ck@d00 ti,gate-clock},­y 8->-omap_54m_fck@d40  ti,mux-clock}-.­y @88>8cm_96m_d2_fck fixed-factor-clock}*û8/>/omap_48m_fck@d40  ti,mux-clock}/.­y @80>0omap_12m_fck fixed-factor-clock}0û8G>Gdpll4_m4_ck@e40 ti,divider-clock}Ù y@ä81>1dpll4_m4x2_mul_ck ti,fixed-factor-clock}1&4A82>2dpll4_m4x2_ck@d00 ti,gate-clock}2­y A8‰>‰dpll4_m5_ck@f40 ti,divider-clock}Ù?y@ä83>3dpll4_m5x2_mul_ck ti,fixed-factor-clock}3&4A84>4dpll4_m5x2_ck@d00 ti,gate-clock}4­y A8j>jdpll4_m6_ck@1140 ti,divider-clock}­Ù?y@ä85>5dpll4_m6x2_mul_ck fixed-factor-clock}5û86>6dpll4_m6x2_ck@d00 ti,gate-clock}6­y 87>7emu_per_alwon_ck fixed-factor-clock}7û8c>cclkout2_src_gate_ck@d70  ti,composite-no-wait-gate-clock}&­y p89>9clkout2_src_mux_ck@d70 ti,composite-mux-clock}&*8y p8:>:clkout2_src_ck ti,composite-clock}9:8;>;sys_clkout2@d70 ti,divider-clock};­Ù@y pTmpu_ck fixed-factor-clock}<û8=>=arm_fck@924 ti,divider-clock}=y $Ùemu_mpu_alwon_ck fixed-factor-clock}=û8d>dl3_ick@a40 ti,divider-clock}&Ùy @ä8>>>l4_ick@a40 ti,divider-clock}>­Ùy @ä8?>?rm_ick@c40 ti,divider-clock}?­Ùy @ägpt10_gate_fck@a00 ti,composite-gate-clock}­ y 8A>Agpt10_mux_fck@a40 ti,composite-mux-clock}@­y @8B>Bgpt10_fck ti,composite-clock}ABgpt11_gate_fck@a00 ti,composite-gate-clock}­ y 8C>Cgpt11_mux_fck@a40 ti,composite-mux-clock}@­y @8D>Dgpt11_fck ti,composite-clock}CDcore_96m_fck fixed-factor-clock}Eû8>mmchs2_fck@a00 ti,wait-gate-clock}y ­8´>´mmchs1_fck@a00 ti,wait-gate-clock}y ­8µ>µi2c3_fck@a00 ti,wait-gate-clock}y ­8¶>¶i2c2_fck@a00 ti,wait-gate-clock}y ­8·>·i2c1_fck@a00 ti,wait-gate-clock}y ­8¸>¸mcbsp5_gate_fck@a00 ti,composite-gate-clock}­ y 8>mcbsp1_gate_fck@a00 ti,composite-gate-clock}­ y 8 > core_48m_fck fixed-factor-clock}0û8F>Fmcspi4_fck@a00 ti,wait-gate-clock}Fy ­8¹>¹mcspi3_fck@a00 ti,wait-gate-clock}Fy ­8º>ºmcspi2_fck@a00 ti,wait-gate-clock}Fy ­8»>»mcspi1_fck@a00 ti,wait-gate-clock}Fy ­8¼>¼uart2_fck@a00 ti,wait-gate-clock}Fy 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y8^>^gpt9_mux_fck@1040 ti,composite-mux-clock}@­y@8_>_gpt9_fck ti,composite-clock}^_per_32k_alwon_fck fixed-factor-clock}@û8`>`gpio6_dbck@1000 ti,gate-clock}`y­8�>�gpio5_dbck@1000 ti,gate-clock}`y­8Ž>Žgpio4_dbck@1000 ti,gate-clock}`y­8�>�gpio3_dbck@1000 ti,gate-clock}`y­8�>�gpio2_dbck@1000 ti,gate-clock}`y­ 8‘>‘wdt3_fck@1000 ti,wait-gate-clock}`y­ 8’>’per_l4_ick fixed-factor-clock}?û8a>agpio6_ick@1010 ti,omap3-interface-clock}ay­8“>“gpio5_ick@1010 ti,omap3-interface-clock}ay­8”>”gpio4_ick@1010 ti,omap3-interface-clock}ay­8•>•gpio3_ick@1010 ti,omap3-interface-clock}ay­8–>–gpio2_ick@1010 ti,omap3-interface-clock}ay­ 8—>—wdt3_ick@1010 ti,omap3-interface-clock}ay­ 8˜>˜uart3_ick@1010 ti,omap3-interface-clock}ay­ 8™>™uart4_ick@1010 ti,omap3-interface-clock}ay­8š>šgpt9_ick@1010 ti,omap3-interface-clock}ay­ 8›>›gpt8_ick@1010 ti,omap3-interface-clock}ay­ 8œ>œgpt7_ick@1010 ti,omap3-interface-clock}ay­8�>�gpt6_ick@1010 ti,omap3-interface-clock}ay­8ž>žgpt5_ick@1010 ti,omap3-interface-clock}ay­8Ÿ>Ÿgpt4_ick@1010 ti,omap3-interface-clock}ay­8 > gpt3_ick@1010 ti,omap3-interface-clock}ay­8¡>¡gpt2_ick@1010 ti,omap3-interface-clock}ay­8¢>¢mcbsp2_ick@1010 ti,omap3-interface-clock}ay­8£>£mcbsp3_ick@1010 ti,omap3-interface-clock}ay­8¤>¤mcbsp4_ick@1010 ti,omap3-interface-clock}ay­8¥>¥mcbsp2_gate_fck@1000 ti,composite-gate-clock}­y8 > mcbsp3_gate_fck@1000 ti,composite-gate-clock}­y8>mcbsp4_gate_fck@1000 ti,composite-gate-clock}­y8>emu_src_mux_ck@1140  ti,mux-clock}bcdy@8e>eemu_src_ck ti,clkdm-gate-clock}e8f>fpclk_fck@1140 ti,divider-clock}f­Ùy@äpclkx2_fck@1140 ti,divider-clock}f­Ùy@äatclk_fck@1140 ti,divider-clock}f­Ùy@ätraceclk_src_fck@1140  ti,mux-clock}bcd­y@8g>gtraceclk_fck@1140 ti,divider-clock}g­ Ùy@äsecure_32k_fck  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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-masklinux,phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0ti,use_poweroffbci3v1-supplyregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourcependown-gpioti,dual-voltpbias-supplyvmmc-supplybus-widthstatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-pslabelmultipointnum-epsram-bitsinterface-typeusb-phypowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsgpioslinux,codedefault-onstartup-delay-uspower-supplyenable-gpiosreset-gpiosmode-gpios