Ð þíü©8õ\(Mõ$)isee,omap3-igep0030ti,omap36xxti,omap3 +*7IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)chosen=/ocp@68000000/serial@49020000aliasesI/ocp@68000000/i2c@48070000N/ocp@68000000/i2c@48072000S/ocp@68000000/i2c@48060000X/ocp@68000000/serial@4806a000`/ocp@68000000/serial@4806c000h/ocp@68000000/serial@49020000p/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8xcpu„ˆ�cpu›“à©“às 'ÀO€ 57Èpmu@54000000arm,cortex-a8-pmu„T€ºÅdebugsssocti,omap-inframpu ti,omap3-mpuÅmpuiva ti,iva2.2Åivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus„hº +ÏÅl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ ÏHscm@2000ti,omap3-scmsimple-bus„ + Ï pinmux@30 ti,omap3-padconfpinctrl-single„08+Öçüÿ7defaultEpinmux_uart1_pinsORLcäiäpinmux_uart3_pinsOnpcæiæpinmux_mcbsp2_pins O cùiùpinmux_mmc1_pins0Ocïiïpinmux_mmc2_pins0O(*,.02cóiópinmux_i2c1_pinsOŠŒcçiçpinmux_i2c3_pinsO’”cíiípinmux_twl4030_pinsO°Acèièpinmux_hsusb2_pins0O¤ ¦ ¨ ª ¬ ® cipinmux_uart2_pins O<>@Bcåiåpinmux_lbee1usjyc_pinsO68:côiôscm_conf@270sysconsimple-bus„p0+ Ïp0cipbias_regulator@2b0ti,pbias-omap3ti,pbias-omap„°qpbias_mmc_omap2430xpbias_mmc_omap2430‡w@Ÿ-ÆÀcîiîclocks+mcbsp5_mux_fck@68·ti,composite-mux-clockˆÄ„hcimcbsp5_fck·ti,composite-clockˆcüiümcbsp1_mux_fck@4·ti,composite-mux-clockˆÄ„c i mcbsp1_fck·ti,composite-clockˆ c÷i÷mcbsp2_mux_fck@4·ti,composite-mux-clockˆ Ä„c i mcbsp2_fck·ti,composite-clockˆ cøiømcbsp3_mux_fck@68·ti,composite-mux-clockˆ „hcimcbsp3_fck·ti,composite-clockˆcúiúmcbsp4_mux_fck@68·ti,composite-mux-clockˆ Ä„hcimcbsp4_fck·ti,composite-clockˆcûiûclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single„ \+Öçüÿpinmux_twl4030_vpins Océiéaes@480c5000 ti,omap3-aesÅaes„H PPºÑABÖtxrxprm@48306000 ti,omap3-prm„H0`@º clocks+virt_16_8m_ck· fixed-clockàYciosc_sys_ck@d40· ti,mux-clockˆ„ @cisys_ck@1270·ti,divider-clockˆÄð„pûcisys_clkout1@d70·ti,gate-clockˆ„ pÄdpll3_x2_ck·fixed-factor-clockˆdpll3_m2x2_ck·fixed-factor-clockˆcidpll4_x2_ck·fixed-factor-clockˆcorex2_fck·fixed-factor-clockˆciwkup_l4_ick·fixed-factor-clockˆcNiNcorex2_d3_fck·fixed-factor-clockˆc…i…corex2_d5_fck·fixed-factor-clockˆc†i†clockdomainscm@48004000 ti,omap3-cm„H@@clocks+dummy_apb_pclk· fixed-clockàomap_32k_fck· fixed-clockà€c@i@virt_12m_ck· fixed-clockà·civirt_13m_ck· fixed-clockàÆ]@civirt_19200000_ck· fixed-clockà$øcivirt_26000000_ck· fixed-clockàŒº€civirt_38_4m_ck· fixed-clockàIðcidpll4_ck@d00·ti,omap3-dpll-per-j-type-clockˆ„ D 0cidpll4_m2_ck@d48·ti,divider-clockˆð?„ Hûc i dpll4_m2x2_mul_ck·fixed-factor-clockˆ c!i!dpll4_m2x2_ck@d00·ti,hsdiv-gate-clockˆ!Ä„ 'c"i"omap_96m_alwon_fck·fixed-factor-clockˆ"c)i)dpll3_ck@d00·ti,omap3-dpll-core-clockˆ„ @ 0cidpll3_m3_ck@1140·ti,divider-clockˆÄð„@ûc#i#dpll3_m3x2_mul_ck·fixed-factor-clockˆ#c$i$dpll3_m3x2_ck@d00·ti,hsdiv-gate-clockˆ$Ä „ 'c%i%emu_core_alwon_ck·fixed-factor-clockˆ%cbibsys_altclk· fixed-clockàc.i.mcbsp_clks· fixed-clockàcidpll3_m2_ck@d40·ti,divider-clockˆÄð„ @ûcicore_ck·fixed-factor-clockˆc&i&dpll1_fck@940·ti,divider-clockˆ&Äð„ @ûc'i'dpll1_ck@904·ti,omap3-dpll-clockˆ'„  $ @ 4cidpll1_x2_ck·fixed-factor-clockˆc(i(dpll1_x2m2_ck@944·ti,divider-clockˆ(ð„ Dûc<i<cm_96m_fck·fixed-factor-clockˆ)c*i*omap_96m_fck@d40· ti,mux-clockˆ*Ä„ @cEiEdpll4_m3_ck@e40·ti,divider-clockˆÄð „@ûc+i+dpll4_m3x2_mul_ck·fixed-factor-clockˆ+c,i,dpll4_m3x2_ck@d00·ti,hsdiv-gate-clockˆ,Ä„ 'c-i-omap_54m_fck@d40· ti,mux-clockˆ-.Ä„ @c8i8cm_96m_d2_fck·fixed-factor-clockˆ*c/i/omap_48m_fck@d40· ti,mux-clockˆ/.Ä„ @c0i0omap_12m_fck·fixed-factor-clockˆ0cGiGdpll4_m4_ck@e40·ti,divider-clockˆð „@ûc1i1dpll4_m4x2_mul_ck·ti,fixed-factor-clockˆ1=KXc2i2dpll4_m4x2_ck@d00·ti,gate-clockˆ2Ä„ 'Xc‰i‰dpll4_m5_ck@f40·ti,divider-clockˆð?„@ûc3i3dpll4_m5x2_mul_ck·ti,fixed-factor-clockˆ3=KXc4i4dpll4_m5x2_ck@d00·ti,hsdiv-gate-clockˆ4Ä„ 'Xcjijdpll4_m6_ck@1140·ti,divider-clockˆÄð?„@ûc5i5dpll4_m6x2_mul_ck·fixed-factor-clockˆ5c6i6dpll4_m6x2_ck@d00·ti,hsdiv-gate-clockˆ6Ä„ 'c7i7emu_per_alwon_ck·fixed-factor-clockˆ7ccicclkout2_src_gate_ck@d70· ti,composite-no-wait-gate-clockˆ&Ä„ pc9i9clkout2_src_mux_ck@d70·ti,composite-mux-clockˆ&*8„ pc:i:clkout2_src_ck·ti,composite-clockˆ9:c;i;sys_clkout2@d70·ti,divider-clockˆ;Äð@„ pkmpu_ck·fixed-factor-clockˆ<c=i=arm_fck@924·ti,divider-clockˆ=„ $ðemu_mpu_alwon_ck·fixed-factor-clockˆ=cdidl3_ick@a40·ti,divider-clockˆ&ð„ @ûc>i>l4_ick@a40·ti,divider-clockˆ>Äð„ @ûc?i?rm_ick@c40·ti,divider-clockˆ?Äð„ @ûgpt10_gate_fck@a00·ti,composite-gate-clockˆÄ „ cAiAgpt10_mux_fck@a40·ti,composite-mux-clockˆ@Ä„ @cBiBgpt10_fck·ti,composite-clockˆABgpt11_gate_fck@a00·ti,composite-gate-clockˆÄ „ cCiCgpt11_mux_fck@a40·ti,composite-mux-clockˆ@Ä„ @cDiDgpt11_fck·ti,composite-clockˆCDcore_96m_fck·fixed-factor-clockˆEcimmchs2_fck@a00·ti,wait-gate-clockˆ„ Äcµiµmmchs1_fck@a00·ti,wait-gate-clockˆ„ Äc¶i¶i2c3_fck@a00·ti,wait-gate-clockˆ„ Äc·i·i2c2_fck@a00·ti,wait-gate-clockˆ„ Äc¸i¸i2c1_fck@a00·ti,wait-gate-clockˆ„ Äc¹i¹mcbsp5_gate_fck@a00·ti,composite-gate-clockˆÄ „ cimcbsp1_gate_fck@a00·ti,composite-gate-clockˆÄ „ c i core_48m_fck·fixed-factor-clockˆ0cFiFmcspi4_fck@a00·ti,wait-gate-clockˆF„ Äcºiºmcspi3_fck@a00·ti,wait-gate-clockˆF„ Äc»i»mcspi2_fck@a00·ti,wait-gate-clockˆF„ Äc¼i¼mcspi1_fck@a00·ti,wait-gate-clockˆF„ Äc½i½uart2_fck@a00·ti,wait-gate-clockˆF„ Äc¾i¾uart1_fck@a00·ti,wait-gate-clockˆF„ Ä c¿i¿core_12m_fck·fixed-factor-clockˆGcHiHhdq_fck@a00·ti,wait-gate-clockˆH„ ÄcÀiÀcore_l3_ick·fixed-factor-clockˆ>cIiIsdrc_ick@a10·ti,wait-gate-clockˆI„ ÄcŠiŠgpmc_fck·fixed-factor-clockˆIcore_l4_ick·fixed-factor-clockˆ?cJiJmmchs2_ick@a10·ti,omap3-interface-clockˆJ„ ÄcÁiÁmmchs1_ick@a10·ti,omap3-interface-clockˆJ„ ÄcÂiÂhdq_ick@a10·ti,omap3-interface-clockˆJ„ ÄcÃiÃmcspi4_ick@a10·ti,omap3-interface-clockˆJ„ ÄcÄiÄmcspi3_ick@a10·ti,omap3-interface-clockˆJ„ ÄcÅiÅmcspi2_ick@a10·ti,omap3-interface-clockˆJ„ ÄcÆiÆmcspi1_ick@a10·ti,omap3-interface-clockˆJ„ ÄcÇiÇi2c3_ick@a10·ti,omap3-interface-clockˆJ„ ÄcÈiÈi2c2_ick@a10·ti,omap3-interface-clockˆJ„ ÄcÉiÉi2c1_ick@a10·ti,omap3-interface-clockˆJ„ ÄcÊiÊuart2_ick@a10·ti,omap3-interface-clockˆJ„ ÄcËiËuart1_ick@a10·ti,omap3-interface-clockˆJ„ Ä cÌiÌgpt11_ick@a10·ti,omap3-interface-clockˆJ„ Ä cÍiÍgpt10_ick@a10·ti,omap3-interface-clockˆJ„ Ä cÎiÎmcbsp5_ick@a10·ti,omap3-interface-clockˆJ„ Ä cÏiÏmcbsp1_ick@a10·ti,omap3-interface-clockˆJ„ Ä cÐiÐomapctrl_ick@a10·ti,omap3-interface-clockˆJ„ ÄcÑiÑdss_tv_fck@e00·ti,gate-clockˆ8„Äc°i°dss_96m_fck@e00·ti,gate-clockˆE„Äc±i±dss2_alwon_fck@e00·ti,gate-clockˆ„Äc²i²dummy_ck· fixed-clockàgpt1_gate_fck@c00·ti,composite-gate-clockˆÄ„ cKiKgpt1_mux_fck@c40·ti,composite-mux-clockˆ@„ @cLiLgpt1_fck·ti,composite-clockˆKLaes2_ick@a10·ti,omap3-interface-clockˆJÄ„ cÒiÒwkup_32k_fck·fixed-factor-clockˆ@cMiMgpio1_dbck@c00·ti,gate-clockˆM„ Äc§i§sha12_ick@a10·ti,omap3-interface-clockˆJ„ ÄcÓiÓwdt2_fck@c00·ti,wait-gate-clockˆM„ Äc¨i¨wdt2_ick@c10·ti,omap3-interface-clockˆN„ Äc©i©wdt1_ick@c10·ti,omap3-interface-clockˆN„ Äcªiªgpio1_ick@c10·ti,omap3-interface-clockˆN„ Äc«i«omap_32ksync_ick@c10·ti,omap3-interface-clockˆN„ Äc¬i¬gpt12_ick@c10·ti,omap3-interface-clockˆN„ Äc­i­gpt1_ick@c10·ti,omap3-interface-clockˆN„ Äc®i®per_96m_fck·fixed-factor-clockˆ)c i per_48m_fck·fixed-factor-clockˆ0cOiOuart3_fck@1000·ti,wait-gate-clockˆO„Ä cŒiŒgpt2_gate_fck@1000·ti,composite-gate-clockˆÄ„cPiPgpt2_mux_fck@1040·ti,composite-mux-clockˆ@„@cQiQgpt2_fck·ti,composite-clockˆPQgpt3_gate_fck@1000·ti,composite-gate-clockˆÄ„cRiRgpt3_mux_fck@1040·ti,composite-mux-clockˆ@Ä„@cSiSgpt3_fck·ti,composite-clockˆRSgpt4_gate_fck@1000·ti,composite-gate-clockˆÄ„cTiTgpt4_mux_fck@1040·ti,composite-mux-clockˆ@Ä„@cUiUgpt4_fck·ti,composite-clockˆTUgpt5_gate_fck@1000·ti,composite-gate-clockˆÄ„cViVgpt5_mux_fck@1040·ti,composite-mux-clockˆ@Ä„@cWiWgpt5_fck·ti,composite-clockˆVWgpt6_gate_fck@1000·ti,composite-gate-clockˆÄ„cXiXgpt6_mux_fck@1040·ti,composite-mux-clockˆ@Ä„@cYiYgpt6_fck·ti,composite-clockˆXYgpt7_gate_fck@1000·ti,composite-gate-clockˆÄ„cZiZgpt7_mux_fck@1040·ti,composite-mux-clockˆ@Ä„@c[i[gpt7_fck·ti,composite-clockˆZ[gpt8_gate_fck@1000·ti,composite-gate-clockˆÄ „c\i\gpt8_mux_fck@1040·ti,composite-mux-clockˆ@Ä„@c]i]gpt8_fck·ti,composite-clockˆ\]gpt9_gate_fck@1000·ti,composite-gate-clockˆÄ „c^i^gpt9_mux_fck@1040·ti,composite-mux-clockˆ@Ä„@c_i_gpt9_fck·ti,composite-clockˆ^_per_32k_alwon_fck·fixed-factor-clockˆ@c`i`gpio6_dbck@1000·ti,gate-clockˆ`„Äc�i�gpio5_dbck@1000·ti,gate-clockˆ`„ÄcŽiŽgpio4_dbck@1000·ti,gate-clockˆ`„Äc�i�gpio3_dbck@1000·ti,gate-clockˆ`„Äc�i�gpio2_dbck@1000·ti,gate-clockˆ`„Ä c‘i‘wdt3_fck@1000·ti,wait-gate-clockˆ`„Ä c’i’per_l4_ick·fixed-factor-clockˆ?caiagpio6_ick@1010·ti,omap3-interface-clockˆa„Äc“i“gpio5_ick@1010·ti,omap3-interface-clockˆa„Äc”i”gpio4_ick@1010·ti,omap3-interface-clockˆa„Äc•i•gpio3_ick@1010·ti,omap3-interface-clockˆa„Äc–i–gpio2_ick@1010·ti,omap3-interface-clockˆa„Ä c—i—wdt3_ick@1010·ti,omap3-interface-clockˆa„Ä c˜i˜uart3_ick@1010·ti,omap3-interface-clockˆa„Ä c™i™uart4_ick@1010·ti,omap3-interface-clockˆa„Äcšišgpt9_ick@1010·ti,omap3-interface-clockˆa„Ä c›i›gpt8_ick@1010·ti,omap3-interface-clockˆa„Ä cœiœgpt7_ick@1010·ti,omap3-interface-clockˆa„Äc�i�gpt6_ick@1010·ti,omap3-interface-clockˆa„Äcžižgpt5_ick@1010·ti,omap3-interface-clockˆa„ÄcŸiŸgpt4_ick@1010·ti,omap3-interface-clockˆa„Äc i gpt3_ick@1010·ti,omap3-interface-clockˆa„Äc¡i¡gpt2_ick@1010·ti,omap3-interface-clockˆa„Äc¢i¢mcbsp2_ick@1010·ti,omap3-interface-clockˆa„Äc£i£mcbsp3_ick@1010·ti,omap3-interface-clockˆa„Äc¤i¤mcbsp4_ick@1010·ti,omap3-interface-clockˆa„Äc¥i¥mcbsp2_gate_fck@1000·ti,composite-gate-clockˆÄ„c i mcbsp3_gate_fck@1000·ti,composite-gate-clockˆÄ„cimcbsp4_gate_fck@1000·ti,composite-gate-clockˆÄ„ciemu_src_mux_ck@1140· ti,mux-clockˆbcd„@ceieemu_src_ck·ti,clkdm-gate-clockˆecfifpclk_fck@1140·ti,divider-clockˆfÄð„@ûpclkx2_fck@1140·ti,divider-clockˆfÄð„@ûatclk_fck@1140·ti,divider-clockˆfÄð„@ûtraceclk_src_fck@1140· ti,mux-clockˆbcdÄ„@cgigtraceclk_fck@1140·ti,divider-clockˆgÄ ð„@ûsecure_32k_fck· fixed-clockà€chihgpt12_fck·fixed-factor-clockˆhwdt1_fck·fixed-factor-clockˆhsecurity_l4_ick2·fixed-factor-clockˆ?ciiiaes1_ick@a14·ti,omap3-interface-clockˆiÄ„ rng_ick@a14·ti,omap3-interface-clockˆi„ Äsha11_ick@a14·ti,omap3-interface-clockˆi„ Ädes1_ick@a14·ti,omap3-interface-clockˆi„ Äcam_mclk@f00·ti,gate-clockˆjÄ„Xcam_ick@f10·!ti,omap3-no-wait-interface-clockˆ?„ÄcÚiÚcsi2_96m_fck@f00·ti,gate-clockˆ„ÄcÛiÛsecurity_l3_ick·fixed-factor-clockˆ>ckikpka_ick@a14·ti,omap3-interface-clockˆk„ Äicr_ick@a10·ti,omap3-interface-clockˆJ„ Ädes2_ick@a10·ti,omap3-interface-clockˆJ„ Ämspro_ick@a10·ti,omap3-interface-clockˆJ„ Ämailboxes_ick@a10·ti,omap3-interface-clockˆJ„ Ässi_l4_ick·fixed-factor-clockˆ?crirsr1_fck@c00·ti,wait-gate-clockˆ„ Äsr2_fck@c00·ti,wait-gate-clockˆ„ Äsr_l4_ick·fixed-factor-clockˆ?dpll2_fck@40·ti,divider-clockˆ&Äð„@ûclildpll2_ck@4·ti,omap3-dpll-clockˆl„$@4�“›cmimdpll2_m2_ck@44·ti,divider-clockˆmð„Dûcniniva2_ck@0·ti,wait-gate-clockˆn„ÄcÜiÜmodem_fck@a00·ti,omap3-interface-clockˆ„ ÄcÝiÝsad2d_ick@a10·ti,omap3-interface-clockˆ>„ ÄcÞiÞmad2d_ick@a18·ti,omap3-interface-clockˆ>„ Äcßißmspro_fck@a00·ti,wait-gate-clockˆ„ Ässi_ssr_gate_fck_3430es2@a00· ti,composite-no-wait-gate-clockˆÄ„ coiossi_ssr_div_fck_3430es2@a40·ti,composite-divider-clockˆÄ„ @$¯cpipssi_ssr_fck_3430es2·ti,composite-clockˆopcqiqssi_sst_fck_3430es2·fixed-factor-clockˆqcihsotgusb_ick_3430es2@a10·"ti,omap3-hsotgusb-interface-clockˆI„ Äc‹i‹ssi_ick_3430es2@a10·ti,omap3-ssi-interface-clockˆr„ Äciusim_gate_fck@c00·ti,composite-gate-clockˆEÄ „ c}i}sys_d2_ck·fixed-factor-clockˆctitomap_96m_d2_fck·fixed-factor-clockˆEcuiuomap_96m_d4_fck·fixed-factor-clockˆEcvivomap_96m_d8_fck·fixed-factor-clockˆEcwiwomap_96m_d10_fck·fixed-factor-clockˆE cxixdpll5_m2_d4_ck·fixed-factor-clockˆscyiydpll5_m2_d8_ck·fixed-factor-clockˆsczizdpll5_m2_d16_ck·fixed-factor-clockˆsc{i{dpll5_m2_d20_ck·fixed-factor-clockˆsc|i|usim_mux_fck@c40·ti,composite-mux-clock(ˆtuvwxyz{|Ä„ @ûc~i~usim_fck·ti,composite-clockˆ}~usim_ick@c10·ti,omap3-interface-clockˆN„ Ä c¯i¯dpll5_ck@d04·ti,omap3-dpll-clockˆ„  $ L 4�“cidpll5_m2_ck@d50·ti,divider-clockˆð„ Pûcsissgx_gate_fck@b00·ti,composite-gate-clockˆ&Ä„ c‡i‡core_d3_ck·fixed-factor-clockˆ&c€i€core_d4_ck·fixed-factor-clockˆ&c�i�core_d6_ck·fixed-factor-clockˆ&c‚i‚omap_192m_alwon_fck·fixed-factor-clockˆ"cƒiƒcore_d2_ck·fixed-factor-clockˆ&c„i„sgx_mux_fck@b40·ti,composite-mux-clock ˆ€�‚*ƒ„…†„ @cˆiˆsgx_fck·ti,composite-clockˆ‡ˆsgx_ick@b10·ti,wait-gate-clockˆ>„ Äcàiàcpefuse_fck@a08·ti,gate-clockˆ„ ÄcÔiÔts_fck@a08·ti,gate-clockˆ@„ ÄcÕiÕusbtll_fck@a08·ti,wait-gate-clockˆs„ ÄcÖiÖusbtll_ick@a18·ti,omap3-interface-clockˆJ„ Äc×i×mmchs3_ick@a10·ti,omap3-interface-clockˆJ„ ÄcØiØmmchs3_fck@a00·ti,wait-gate-clockˆ„ ÄcÙiÙdss1_alwon_fck_3430es2@e00·ti,dss-gate-clockˆ‰Ä„Xc³i³dss_ick_3430es2@e10·ti,omap3-dss-interface-clockˆ?„Äc´i´usbhost_120m_fck@1400·ti,gate-clockˆs„Äcáiáusbhost_48m_fck@1400·ti,dss-gate-clockˆ0„Äcâiâusbhost_ick@1410·ti,omap3-dss-interface-clockˆ?„Äcãiãuart4_fck@1000·ti,wait-gate-clockˆO„Äc¦i¦clockdomainscore_l3_clkdmti,clockdomainˆŠ‹dpll3_clkdmti,clockdomainˆdpll1_clkdmti,clockdomainˆper_clkdmti,clockdomainlˆŒ�Ž��‘’“”•–—˜™š›œ�žŸ ¡¢£¤¥¦emu_clkdmti,clockdomainˆfdpll4_clkdmti,clockdomainˆwkup_clkdmti,clockdomain$ˆ§¨©ª«¬­®¯dss_clkdmti,clockdomainˆ°±²³´core_l4_clkdmti,clockdomain”ˆµ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖרÙcam_clkdmti,clockdomainˆÚÛiva2_clkdmti,clockdomainˆÜdpll2_clkdmti,clockdomainˆmd2d_clkdmti,clockdomain ˆÝÞßdpll5_clkdmti,clockdomainˆsgx_clkdmti,clockdomainˆàusbhost_clkdmti,clockdomain ˆáâãcounter@48320000ti,omap-counter32k„H2  Åcounter_32kinterrupt-controller@48200000ti,omap3-intcçÖ„H cidma-controller@48056000"ti,omap3630-sdmati,omap3430-sdma„H`º »Æ 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compatibleinterrupt-parent#address-cells#size-cellsmodelstdout-pathi2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthcd-gpiosmmc-pwrseqnon-removablestatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-modephysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsti,modelti,mcbspregulator-always-ondefault-statereset-gpios