Ð þíÿ8õH( ¾õ timll,omap3-devkit8000ti,omap3 +,7TimLL OMAP3 Devkit8000 with 7.0'' LCD panelchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/display m/connector0 v/connector1cpus+cpu@0arm,cortex-a8cpu‹�–cpu¢“à(°èHà˜Ð�g8¡ O€dp`ð 'À™ppmu@54000000arm,cortex-a8-pmu‹T€ÁÌdebugsssocti,omap-inframpu ti,omap3-mpuÌmpuiva ti,iva2.2Ìivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus‹hÁ +ÖÌl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ ÖHscm@2000ti,omap3-scmsimple-bus‹ + Ö pinmux@30 ti,omap3-padconfpinctrl-single‹08+Ýî!ÿpinmux_twl4030_pins>°ARâXâpinmux_dss_dpi_pinsà>¤¦¨ª¬®°²´¶¸º¼¾ÀÂÄÆÈÊÌÎÐÒÔÖØÚRòXòscm_conf@270sysconsimple-bus‹p0+ Öp0RXpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap‹°`pbias_mmc_omap2430gpbias_mmc_omap2430vw@Ž-ÆÀRéXéclocks+mcbsp5_mux_fck@68¦ti,composite-mux-clock�³‹hRXmcbsp5_fck¦ti,composite-clock�RðXðmcbsp1_mux_fck@4¦ti,composite-mux-clock�³‹R X mcbsp1_fck¦ti,composite-clock� RìXìmcbsp2_mux_fck@4¦ti,composite-mux-clock� ³‹R X mcbsp2_fck¦ti,composite-clock� RíXímcbsp3_mux_fck@68¦ti,composite-mux-clock� ‹hRXmcbsp3_fck¦ti,composite-clock� RîXîmcbsp4_mux_fck@68¦ti,composite-mux-clock� ³‹hRXmcbsp4_fck¦ti,composite-clock�RïXïclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single‹ \+Ýî!ÿpinmux_twl4030_vpins >RãXãaes@480c5000 ti,omap3-aesÌaes‹H PPÁÀABÅtxrxprm@48306000 ti,omap3-prm‹H0`@Á clocks+virt_16_8m_ck¦ fixed-clockÏYRXosc_sys_ck@d40¦ ti,mux-clock�‹ @RXsys_ck@1270¦ti,divider-clock�³ß‹pêRXsys_clkout1@d70¦ti,gate-clock�‹ p³dpll3_x2_ck¦fixed-factor-clock� dpll3_m2x2_ck¦fixed-factor-clock� RXdpll4_x2_ck¦fixed-factor-clock� corex2_fck¦fixed-factor-clock� RXwkup_l4_ick¦fixed-factor-clock� RMXMcorex2_d3_fck¦fixed-factor-clock� R„X„corex2_d5_fck¦fixed-factor-clock� R…X…clockdomainscm@48004000 ti,omap3-cm‹H@@clocks+dummy_apb_pclk¦ fixed-clockÏomap_32k_fck¦ fixed-clockÏ€R?X?virt_12m_ck¦ fixed-clockÏ·RXvirt_13m_ck¦ fixed-clockÏÆ]@RXvirt_19200000_ck¦ fixed-clockÏ$øRXvirt_26000000_ck¦ fixed-clockÏŒº€RXvirt_38_4m_ck¦ fixed-clockÏIðRXdpll4_ck@d00¦ti,omap3-dpll-per-clock�‹ D 0RXdpll4_m2_ck@d48¦ti,divider-clock�ß?‹ HêRXdpll4_m2x2_mul_ck¦fixed-factor-clock� R X dpll4_m2x2_ck@d00¦ti,gate-clock� ³‹ R!X!omap_96m_alwon_fck¦fixed-factor-clock�! R(X(dpll3_ck@d00¦ti,omap3-dpll-core-clock�‹ @ 0RXdpll3_m3_ck@1140¦ti,divider-clock�³ß‹@êR"X"dpll3_m3x2_mul_ck¦fixed-factor-clock�" R#X#dpll3_m3x2_ck@d00¦ti,gate-clock�#³ ‹ R$X$emu_core_alwon_ck¦fixed-factor-clock�$ RaXasys_altclk¦ fixed-clockÏR-X-mcbsp_clks¦ fixed-clockÏRXdpll3_m2_ck@d40¦ti,divider-clock�³ß‹ @êRXcore_ck¦fixed-factor-clock� R%X%dpll1_fck@940¦ti,divider-clock�%³ß‹ @êR&X&dpll1_ck@904¦ti,omap3-dpll-clock�&‹  $ @ 4RXdpll1_x2_ck¦fixed-factor-clock� R'X'dpll1_x2m2_ck@944¦ti,divider-clock�'ß‹ DêR;X;cm_96m_fck¦fixed-factor-clock�( R)X)omap_96m_fck@d40¦ ti,mux-clock�)³‹ @RDXDdpll4_m3_ck@e40¦ti,divider-clock�³ß ‹@êR*X*dpll4_m3x2_mul_ck¦fixed-factor-clock�* R+X+dpll4_m3x2_ck@d00¦ti,gate-clock�+³‹ R,X,omap_54m_fck@d40¦ ti,mux-clock�,-³‹ @R7X7cm_96m_d2_fck¦fixed-factor-clock�) R.X.omap_48m_fck@d40¦ ti,mux-clock�.-³‹ @R/X/omap_12m_fck¦fixed-factor-clock�/ RFXFdpll4_m4_ck@e40¦ti,divider-clock�ß ‹@êR0X0dpll4_m4x2_mul_ck¦ti,fixed-factor-clock�0,:GR1X1dpll4_m4x2_ck@d00¦ti,gate-clock�1³‹ GRˆXˆdpll4_m5_ck@f40¦ti,divider-clock�ß?‹@êR2X2dpll4_m5x2_mul_ck¦ti,fixed-factor-clock�2,:GR3X3dpll4_m5x2_ck@d00¦ti,gate-clock�3³‹ GRiXidpll4_m6_ck@1140¦ti,divider-clock�³ß?‹@êR4X4dpll4_m6x2_mul_ck¦fixed-factor-clock�4 R5X5dpll4_m6x2_ck@d00¦ti,gate-clock�5³‹ R6X6emu_per_alwon_ck¦fixed-factor-clock�6 RbXbclkout2_src_gate_ck@d70¦ ti,composite-no-wait-gate-clock�%³‹ pR8X8clkout2_src_mux_ck@d70¦ti,composite-mux-clock�%)7‹ pR9X9clkout2_src_ck¦ti,composite-clock�89R:X:sys_clkout2@d70¦ti,divider-clock�:³ß@‹ pZmpu_ck¦fixed-factor-clock�; R<X<arm_fck@924¦ti,divider-clock�<‹ $ßemu_mpu_alwon_ck¦fixed-factor-clock�< RcXcl3_ick@a40¦ti,divider-clock�%ß‹ @êR=X=l4_ick@a40¦ti,divider-clock�=³ß‹ @êR>X>rm_ick@c40¦ti,divider-clock�>³ß‹ @êgpt10_gate_fck@a00¦ti,composite-gate-clock�³ ‹ R@X@gpt10_mux_fck@a40¦ti,composite-mux-clock�?³‹ @RAXAgpt10_fck¦ti,composite-clock�@Agpt11_gate_fck@a00¦ti,composite-gate-clock�³ ‹ RBXBgpt11_mux_fck@a40¦ti,composite-mux-clock�?³‹ @RCXCgpt11_fck¦ti,composite-clock�BCcore_96m_fck¦fixed-factor-clock�D RXmmchs2_fck@a00¦ti,wait-gate-clock�‹ ³R³X³mmchs1_fck@a00¦ti,wait-gate-clock�‹ ³R´X´i2c3_fck@a00¦ti,wait-gate-clock�‹ ³RµXµi2c2_fck@a00¦ti,wait-gate-clock�‹ ³R¶X¶i2c1_fck@a00¦ti,wait-gate-clock�‹ ³R·X·mcbsp5_gate_fck@a00¦ti,composite-gate-clock�³ ‹ RXmcbsp1_gate_fck@a00¦ti,composite-gate-clock�³ ‹ RXcore_48m_fck¦fixed-factor-clock�/ REXEmcspi4_fck@a00¦ti,wait-gate-clock�E‹ ³R¸X¸mcspi3_fck@a00¦ti,wait-gate-clock�E‹ ³R¹X¹mcspi2_fck@a00¦ti,wait-gate-clock�E‹ ³RºXºmcspi1_fck@a00¦ti,wait-gate-clock�E‹ ³R»X»uart2_fck@a00¦ti,wait-gate-clock�E‹ ³R¼X¼uart1_fck@a00¦ti,wait-gate-clock�E‹ ³ R½X½core_12m_fck¦fixed-factor-clock�F RGXGhdq_fck@a00¦ti,wait-gate-clock�G‹ ³R¾X¾core_l3_ick¦fixed-factor-clock�= RHXHsdrc_ick@a10¦ti,wait-gate-clock�H‹ ³R‰X‰gpmc_fck¦fixed-factor-clock�H core_l4_ick¦fixed-factor-clock�> RIXImmchs2_ick@a10¦ti,omap3-interface-clock�I‹ ³R¿X¿mmchs1_ick@a10¦ti,omap3-interface-clock�I‹ ³RÀXÀhdq_ick@a10¦ti,omap3-interface-clock�I‹ ³RÁXÁmcspi4_ick@a10¦ti,omap3-interface-clock�I‹ ³RÂXÂmcspi3_ick@a10¦ti,omap3-interface-clock�I‹ ³RÃXÃmcspi2_ick@a10¦ti,omap3-interface-clock�I‹ ³RÄXÄmcspi1_ick@a10¦ti,omap3-interface-clock�I‹ ³RÅXÅi2c3_ick@a10¦ti,omap3-interface-clock�I‹ ³RÆXÆi2c2_ick@a10¦ti,omap3-interface-clock�I‹ ³RÇXÇi2c1_ick@a10¦ti,omap3-interface-clock�I‹ ³RÈXÈuart2_ick@a10¦ti,omap3-interface-clock�I‹ ³RÉXÉuart1_ick@a10¦ti,omap3-interface-clock�I‹ ³ RÊXÊgpt11_ick@a10¦ti,omap3-interface-clock�I‹ ³ RËXËgpt10_ick@a10¦ti,omap3-interface-clock�I‹ ³ RÌXÌmcbsp5_ick@a10¦ti,omap3-interface-clock�I‹ ³ RÍXÍmcbsp1_ick@a10¦ti,omap3-interface-clock�I‹ ³ RÎXÎomapctrl_ick@a10¦ti,omap3-interface-clock�I‹ ³RÏXÏdss_tv_fck@e00¦ti,gate-clock�7‹³R®X®dss_96m_fck@e00¦ti,gate-clock�D‹³R¯X¯dss2_alwon_fck@e00¦ti,gate-clock�‹³R°X°dummy_ck¦ fixed-clockÏgpt1_gate_fck@c00¦ti,composite-gate-clock�³‹ RJXJgpt1_mux_fck@c40¦ti,composite-mux-clock�?‹ @RKXKgpt1_fck¦ti,composite-clock�JKaes2_ick@a10¦ti,omap3-interface-clock�I³‹ RÐXÐwkup_32k_fck¦fixed-factor-clock�? RLXLgpio1_dbck@c00¦ti,gate-clock�L‹ ³R¥X¥sha12_ick@a10¦ti,omap3-interface-clock�I‹ ³RÑXÑwdt2_fck@c00¦ti,wait-gate-clock�L‹ ³R¦X¦wdt2_ick@c10¦ti,omap3-interface-clock�M‹ ³R§X§wdt1_ick@c10¦ti,omap3-interface-clock�M‹ ³R¨X¨gpio1_ick@c10¦ti,omap3-interface-clock�M‹ ³R©X©omap_32ksync_ick@c10¦ti,omap3-interface-clock�M‹ ³RªXªgpt12_ick@c10¦ti,omap3-interface-clock�M‹ ³R«X«gpt1_ick@c10¦ti,omap3-interface-clock�M‹ ³R¬X¬per_96m_fck¦fixed-factor-clock�( R X per_48m_fck¦fixed-factor-clock�/ RNXNuart3_fck@1000¦ti,wait-gate-clock�N‹³ R‹X‹gpt2_gate_fck@1000¦ti,composite-gate-clock�³‹ROXOgpt2_mux_fck@1040¦ti,composite-mux-clock�?‹@RPXPgpt2_fck¦ti,composite-clock�OPgpt3_gate_fck@1000¦ti,composite-gate-clock�³‹RQXQgpt3_mux_fck@1040¦ti,composite-mux-clock�?³‹@RRXRgpt3_fck¦ti,composite-clock�QRgpt4_gate_fck@1000¦ti,composite-gate-clock�³‹RSXSgpt4_mux_fck@1040¦ti,composite-mux-clock�?³‹@RTXTgpt4_fck¦ti,composite-clock�STgpt5_gate_fck@1000¦ti,composite-gate-clock�³‹RUXUgpt5_mux_fck@1040¦ti,composite-mux-clock�?³‹@RVXVgpt5_fck¦ti,composite-clock�UVgpt6_gate_fck@1000¦ti,composite-gate-clock�³‹RWXWgpt6_mux_fck@1040¦ti,composite-mux-clock�?³‹@RXXXgpt6_fck¦ti,composite-clock�WXgpt7_gate_fck@1000¦ti,composite-gate-clock�³‹RYXYgpt7_mux_fck@1040¦ti,composite-mux-clock�?³‹@RZXZgpt7_fck¦ti,composite-clock�YZgpt8_gate_fck@1000¦ti,composite-gate-clock�³ ‹R[X[gpt8_mux_fck@1040¦ti,composite-mux-clock�?³‹@R\X\gpt8_fck¦ti,composite-clock�[\gpt9_gate_fck@1000¦ti,composite-gate-clock�³ ‹R]X]gpt9_mux_fck@1040¦ti,composite-mux-clock�?³‹@R^X^gpt9_fck¦ti,composite-clock�]^per_32k_alwon_fck¦fixed-factor-clock�? R_X_gpio6_dbck@1000¦ti,gate-clock�_‹³RŒXŒgpio5_dbck@1000¦ti,gate-clock�_‹³R�X�gpio4_dbck@1000¦ti,gate-clock�_‹³RŽXŽgpio3_dbck@1000¦ti,gate-clock�_‹³R�X�gpio2_dbck@1000¦ti,gate-clock�_‹³ R�X�wdt3_fck@1000¦ti,wait-gate-clock�_‹³ R‘X‘per_l4_ick¦fixed-factor-clock�> R`X`gpio6_ick@1010¦ti,omap3-interface-clock�`‹³R’X’gpio5_ick@1010¦ti,omap3-interface-clock�`‹³R“X“gpio4_ick@1010¦ti,omap3-interface-clock�`‹³R”X”gpio3_ick@1010¦ti,omap3-interface-clock�`‹³R•X•gpio2_ick@1010¦ti,omap3-interface-clock�`‹³ R–X–wdt3_ick@1010¦ti,omap3-interface-clock�`‹³ R—X—uart3_ick@1010¦ti,omap3-interface-clock�`‹³ R˜X˜uart4_ick@1010¦ti,omap3-interface-clock�`‹³R™X™gpt9_ick@1010¦ti,omap3-interface-clock�`‹³ RšXšgpt8_ick@1010¦ti,omap3-interface-clock�`‹³ R›X›gpt7_ick@1010¦ti,omap3-interface-clock�`‹³RœXœgpt6_ick@1010¦ti,omap3-interface-clock�`‹³R�X�gpt5_ick@1010¦ti,omap3-interface-clock�`‹³RžXžgpt4_ick@1010¦ti,omap3-interface-clock�`‹³RŸXŸgpt3_ick@1010¦ti,omap3-interface-clock�`‹³R X gpt2_ick@1010¦ti,omap3-interface-clock�`‹³R¡X¡mcbsp2_ick@1010¦ti,omap3-interface-clock�`‹³R¢X¢mcbsp3_ick@1010¦ti,omap3-interface-clock�`‹³R£X£mcbsp4_ick@1010¦ti,omap3-interface-clock�`‹³R¤X¤mcbsp2_gate_fck@1000¦ti,composite-gate-clock�³‹R X mcbsp3_gate_fck@1000¦ti,composite-gate-clock�³‹R X mcbsp4_gate_fck@1000¦ti,composite-gate-clock�³‹RXemu_src_mux_ck@1140¦ ti,mux-clock�abc‹@RdXdemu_src_ck¦ti,clkdm-gate-clock�dReXepclk_fck@1140¦ti,divider-clock�e³ß‹@êpclkx2_fck@1140¦ti,divider-clock�e³ß‹@êatclk_fck@1140¦ti,divider-clock�e³ß‹@êtraceclk_src_fck@1140¦ ti,mux-clock�abc³‹@RfXftraceclk_fck@1140¦ti,divider-clock�f³ ß‹@êsecure_32k_fck¦ fixed-clockÏ€RgXggpt12_fck¦fixed-factor-clock�g wdt1_fck¦fixed-factor-clock�g security_l4_ick2¦fixed-factor-clock�> RhXhaes1_ick@a14¦ti,omap3-interface-clock�h³‹ rng_ick@a14¦ti,omap3-interface-clock�h‹ ³sha11_ick@a14¦ti,omap3-interface-clock�h‹ ³des1_ick@a14¦ti,omap3-interface-clock�h‹ ³cam_mclk@f00¦ti,gate-clock�i³‹Gcam_ick@f10¦!ti,omap3-no-wait-interface-clock�>‹³RØXØcsi2_96m_fck@f00¦ti,gate-clock�‹³RÙXÙsecurity_l3_ick¦fixed-factor-clock�= RjXjpka_ick@a14¦ti,omap3-interface-clock�j‹ ³icr_ick@a10¦ti,omap3-interface-clock�I‹ ³des2_ick@a10¦ti,omap3-interface-clock�I‹ ³mspro_ick@a10¦ti,omap3-interface-clock�I‹ ³mailboxes_ick@a10¦ti,omap3-interface-clock�I‹ ³ssi_l4_ick¦fixed-factor-clock�> RqXqsr1_fck@c00¦ti,wait-gate-clock�‹ ³sr2_fck@c00¦ti,wait-gate-clock�‹ ³sr_l4_ick¦fixed-factor-clock�> dpll2_fck@40¦ti,divider-clock�%³ß‹@êRkXkdpll2_ck@4¦ti,omap3-dpll-clock�k‹$@4p‚ŠRlXldpll2_m2_ck@44¦ti,divider-clock�lß‹DêRmXmiva2_ck@0¦ti,wait-gate-clock�m‹³RÚXÚmodem_fck@a00¦ti,omap3-interface-clock�‹ ³RÛXÛsad2d_ick@a10¦ti,omap3-interface-clock�=‹ ³RÜXÜmad2d_ick@a18¦ti,omap3-interface-clock�=‹ ³RÝXÝmspro_fck@a00¦ti,wait-gate-clock�‹ ³ssi_ssr_gate_fck_3430es2@a00¦ ti,composite-no-wait-gate-clock�³‹ RnXnssi_ssr_div_fck_3430es2@a40¦ti,composite-divider-clock�³‹ @$žRoXossi_ssr_fck_3430es2¦ti,composite-clock�noRpXpssi_sst_fck_3430es2¦fixed-factor-clock�p R÷X÷hsotgusb_ick_3430es2@a10¦"ti,omap3-hsotgusb-interface-clock�H‹ ³RŠXŠssi_ick_3430es2@a10¦ti,omap3-ssi-interface-clock�q‹ ³RøXøusim_gate_fck@c00¦ti,composite-gate-clock�D³ ‹ R|X|sys_d2_ck¦fixed-factor-clock� RsXsomap_96m_d2_fck¦fixed-factor-clock�D RtXtomap_96m_d4_fck¦fixed-factor-clock�D RuXuomap_96m_d8_fck¦fixed-factor-clock�D RvXvomap_96m_d10_fck¦fixed-factor-clock�D RwXwdpll5_m2_d4_ck¦fixed-factor-clock�r RxXxdpll5_m2_d8_ck¦fixed-factor-clock�r RyXydpll5_m2_d16_ck¦fixed-factor-clock�r RzXzdpll5_m2_d20_ck¦fixed-factor-clock�r R{X{usim_mux_fck@c40¦ti,composite-mux-clock(�stuvwxyz{³‹ @êR}X}usim_fck¦ti,composite-clock�|}usim_ick@c10¦ti,omap3-interface-clock�M‹ ³ R­X­dpll5_ck@d04¦ti,omap3-dpll-clock�‹  $ L 4p‚R~X~dpll5_m2_ck@d50¦ti,divider-clock�~ß‹ PêRrXrsgx_gate_fck@b00¦ti,composite-gate-clock�%³‹ R†X†core_d3_ck¦fixed-factor-clock�% RXcore_d4_ck¦fixed-factor-clock�% R€X€core_d6_ck¦fixed-factor-clock�% R�X�omap_192m_alwon_fck¦fixed-factor-clock�! R‚X‚core_d2_ck¦fixed-factor-clock�% RƒXƒsgx_mux_fck@b40¦ti,composite-mux-clock �€�)‚ƒ„…‹ @R‡X‡sgx_fck¦ti,composite-clock�†‡sgx_ick@b10¦ti,wait-gate-clock�=‹ ³RÞXÞcpefuse_fck@a08¦ti,gate-clock�‹ ³RÒXÒts_fck@a08¦ti,gate-clock�?‹ ³RÓXÓusbtll_fck@a08¦ti,wait-gate-clock�r‹ ³RÔXÔusbtll_ick@a18¦ti,omap3-interface-clock�I‹ ³RÕXÕmmchs3_ick@a10¦ti,omap3-interface-clock�I‹ ³RÖXÖmmchs3_fck@a00¦ti,wait-gate-clock�‹ ³R×X×dss1_alwon_fck_3430es2@e00¦ti,dss-gate-clock�ˆ³‹GR±X±dss_ick_3430es2@e10¦ti,omap3-dss-interface-clock�>‹³R²X²usbhost_120m_fck@1400¦ti,gate-clock�r‹³RßXßusbhost_48m_fck@1400¦ti,dss-gate-clock�/‹³RàXàusbhost_ick@1410¦ti,omap3-dss-interface-clock�>‹³RáXáclockdomainscore_l3_clkdmti,clockdomain�‰Šdpll3_clkdmti,clockdomain�dpll1_clkdmti,clockdomain�per_clkdmti,clockdomainh�‹Œ�Ž��‘’“”•–—˜™š›œ�žŸ ¡¢£¤emu_clkdmti,clockdomain�edpll4_clkdmti,clockdomain�wkup_clkdmti,clockdomain$�¥¦§¨©ª«¬­dss_clkdmti,clockdomain�®¯°±²core_l4_clkdmti,clockdomain”�³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×cam_clkdmti,clockdomain�ØÙiva2_clkdmti,clockdomain�Údpll2_clkdmti,clockdomain�ld2d_clkdmti,clockdomain �ÛÜÝdpll5_clkdmti,clockdomain�~sgx_clkdmti,clockdomain�Þusbhost_clkdmti,clockdomain �ßàácounter@48320000ti,omap-counter32k‹H2  Ìcounter_32kinterrupt-controller@48200000ti,omap3-intcîÝ‹H RXdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdma‹H`Á ªµ Â`RXgpio@48310000ti,omap3-gpio‹H1ÁÌgpio1ÏáñîÝRèXègpio@49050000ti,omap3-gpio‹IÁÌgpio2áñîÝgpio@49052000ti,omap3-gpio‹I ÁÌgpio3áñîÝgpio@49054000ti,omap3-gpio‹I@Á Ìgpio4áñîÝgpio@49056000ti,omap3-gpio‹I`Á!Ìgpio5áñîÝgpio@49058000ti,omap3-gpio‹I€Á"Ìgpio6áñîÝRúXúserial@4806a000ti,omap3-uart‹H  ýHÀ12ÅtxrxÌuart1ÏÜlserial@4806c000ti,omap3-uart‹HÀýIÀ34ÅtxrxÌuart2ÏÜlserial@49020000ti,omap3-uart‹IýJÀ56ÅtxrxÌuart3ÏÜli2c@48070000 ti,omap3-i2c‹H€Á8ÀÅtxrx+Ìi2c1Ï'¬@twl@48‹HÁ ti,twl4030îÝdefaultâãaudioti,twl4030-audiocodecrtcti,twl4030-rtcÁ bciti,twl4030-bciÁ )äwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1v 'ÀŽ regulator-vdacti,twl4030-vdacvw@Žw@RôXôregulator-vioti,twl4030-viovw@Žw@RçXçregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1v:�Ž0°RêXêregulator-vmmc2ti,twl4030-vmmc2v:�Ž0°regulator-vusb1v5ti,twl4030-vusb1v5RåXåregulator-vusb1v8ti,twl4030-vusb1v8RæXæregulator-vusb3v1ti,twl4030-vusb3v1RäXäregulator-vpll1ti,twl4030-vpll1 gvdds_dsivw@Žw@RóXóregulator-vpll2ti,twl4030-vpll2vw@Žw@regulator-vsimti,twl4030-vsimvw@Ž-ÆÀRëXëgpioti,twl4030-gpioáñîÝ7C¡ÆRûXûtwl4030-usbti,twl4030-usbÁ På^æläzƒpwmti,twl4030-pwmŽpwmledti,twl4030-pwmledŽpwrbuttonti,twl4030-pwrbuttonÁkeypadti,twl4030-keypadÁ™©D¼?  @A Bsrmadcti,twl4030-madcÁÉi2c@48072000 ti,omap3-i2c‹H €Á9ÀÅtxrx+Ìi2c2Ï€RÿXÿi2c@48060000 ti,omap3-i2c‹H€Á=ÀÅtxrx+Ìi2c3 Ûdisabledmailbox@48094000ti,omap3-mailboxÌmailbox‹H @Áâîdsp  spi@48098000ti,omap2-mcspi‹H €ÁA+Ìmcspi1(@À#$%&'()* Åtx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspi‹H  ÁB+Ìmcspi2( À+,-.Åtx0rx0tx1rx1ads7846@0 ti,ads78466ç‹Aã` èÁ Sè`iÿr{ÿ„´”ÿ¤ ´ÄÔä–ùspi@480b8000ti,omap2-mcspi‹H €Á[+Ìmcspi3( ÀÅtx0rx0tx1rx1spi@480ba000ti,omap2-mcspi‹H  Á0+Ìmcspi4(ÀFGÅtx0rx01w@480b2000 ti,omap3-1w‹H Á:Ìhdq1wmmc@4809c000ti,omap3-hsmmc‹H ÀÁSÌmmc1À=>Åtxrxé!ê-ë=mmc@480b4000ti,omap3-hsmmc‹H @ÁVÌmmc2À/0Åtxrx Ûdisabledmmc@480ad000ti,omap3-hsmmc‹H ÐÁ^Ìmmc3ÀMNÅtxrx Ûdisabledmmu@480bd400Gti,omap2-iommu‹H Ô€ÁÌmmu_ispTRùXùmmu@5d000000Gti,omap2-iommu‹]€ÁÌmmu_iva Ûdisabledwdt@48314000 ti,omap3-wdt‹H1@€ Ìwd_timer2 Ûdisabledmcbsp@48074000ti,omap3-mcbsp‹H@ÿdmpu Á;< ncommontxrx~€Ìmcbsp1À Åtxrx�ì–fck Ûdisabledmcbsp@49022000ti,omap3-mcbsp‹I ÿI€ÿ dmpusidetoneÁ>?ncommontxrxsidetone~Ìmcbsp2mcbsp2_sidetoneÀ!"Åtxrx�í¢–fckickÛokayRüXümcbsp@49024000ti,omap3-mcbsp‹I@ÿI ÿ dmpusidetoneÁYZncommontxrxsidetone~€Ìmcbsp3mcbsp3_sidetoneÀÅtxrx�fckick Ûdisabledmcbsp@49026000ti,omap3-mcbsp‹I`ÿdmpu Á67 ncommontxrx~€Ìmcbsp4ÀÅtxrx�ï–fck Ûdisabledmcbsp@48096000ti,omap3-mcbsp‹H `ÿdmpu ÁQR ncommontxrx~€Ìmcbsp5ÀÅtxrx�ð–fck Ûdisabledsham@480c3000ti,omap3-shamÌsham‹H 0dÁ1ÀEÅrxsmartreflex@480cb000ti,omap3-smartreflex-coreÌsmartreflex_core‹H °Ásmartreflex@480c9000ti,omap3-smartreflex-ivaÌsmartreflex_mpu_iva‹H �Átimer@48318000ti,omap3430-timer‹H1€Á%Ìtimer1�timer@49032000ti,omap3430-timer‹I Á&Ìtimer2timer@49034000ti,omap3430-timer‹I@Á'Ìtimer3timer@49036000ti,omap3430-timer‹I`Á(Ìtimer4timer@49038000ti,omap3430-timer‹I€Á)Ìtimer5œtimer@4903a000ti,omap3430-timer‹I Á*Ìtimer6œtimer@4903c000ti,omap3430-timer‹IÀÁ+Ìtimer7œtimer@4903e000ti,omap3430-timer‹IàÁ,Ìtimer8©œtimer@49040000ti,omap3430-timer‹IÁ-Ìtimer9©timer@48086000ti,omap3430-timer‹H`Á.Ìtimer10©timer@48088000ti,omap3430-timer‹H€Á/Ìtimer11©timer@48304000ti,omap3430-timer‹H0@Á_Ìtimer12�¶usbhstll@48062000 ti,usbhs-tll‹H ÁN Ìusb_tll_hsusbhshost@48064000ti,usbhs-host‹H@ Ìusb_host_hs+Öohci@48064400ti,ohci-omap3‹HD ÁLehci@48064800 ti,ehci-omap‹HH ÁMgpmc@6e000000ti,omap3430-gpmcÌgpmc‹nÐÁÀÅrxtxÆÒ+îÝáñÖ,RñXñnand@0,0ti,omap2-nand ‹ ñÁäósw&4,F,Xg"z,�(œ6«@ºRËRÜ(î+x-loader@0 X-Loader‹bootloaders@80000U-Boot‹bootloaders_env@260000 U-Boot Env‹&kernel@280000Kernel‹(@filesystem@680000 File System‹h˜ethernet@0,0davicom,dm9000‹  èÁ)ó;Ic&4´F´Xgz0}6œ¨‹6�¨ºº˺«�™³ZÊZäüîÜusb_otg_hs@480ab000ti,omap3-musb‹H °Á\]nmcdma Ìusb_otg_hs& dss@48050000 ti,omap3-dss‹HÛok Ìdss_core�±–fck+Ödefaultò/ó?ôdispc@48050400ti,omap3-dispc‹HÁ Ìdss_dispc�±–fckencoder@4804fc00 ti,omap3-dsi‹HüHþ@Hÿ dprotophypllÁ Ûdisabled Ìdss_dsi1�±° –fcksys_clkencoder@48050800ti,omap3-rfbi‹H Ûdisabled Ìdss_rfbi�±²–fckickencoder@48050c00ti,omap3-venc‹H Ûok Ìdss_venc�®–fckOôportendpoint[õkRXportendpoint[öwRýXýssi-controller@48058000 ti,omap3-ssiÌssiÛok‹H€H�dsysgddÁGngdd_mpu+Ö �p÷ø –ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-port‹H H¨dtxrx ÁCDssi-port@4805b000ti,omap3-ssi-port‹H°H¸dtxrx ÁEFpinmux@480025d8 ti,omap3-padconfpinctrl-single‹H%Ø$+Ýî!ÿisp@480bc000 ti,omap3-isp‹H ÀüH Ø|Á‚ù`l‰¦ports+bandgap@48002524‹H%$ti,omap34xx-bandgap•memory@80000000memory‹€leds gpio-ledsheartbeatdevkit8000::led1 «ú±on ¿heartbeatmmcdevkit8000::led2 «ú±on¿noneusrdevkit8000::led3 «ú±on¿usrpmu_statdevkit8000::pmu_stat «ûsoundti,omap-twl4030 Õdevkit8000ÞüIçExt SpkPREDRIVELExt SpkPREDRIVERMAINMICMain MicMain MicMic Bias 1gpio_keys gpio-keysuseruser «èøùencoder0 ti,tfp410 ûports+port@0‹endpoint[ýport@1‹endpoint[þRXconnector0dvi-connectordvi  ÿportendpoint[RþXþconnector1svideo-connectortvportendpoint[RõXõdisplay panel-dpilcd 'ûportendpoint[ýRöXöpanel-timingÏbZ 4  <à D Q ]0 g s  € Š — ¤ ® compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0display1display2device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyti,use-ledsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsstatus#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repti,keep-vref-onti,settle-delay-usecwakeup-sourceti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-width#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthdavicom,no-eepromgpmc,mux-add-datagpmc,wait-pingpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsmultipointnum-epsram-bitsvdds_dsi-supplyvdda_dac-supplyvdda-supplyremote-endpointti,channelsdata-linesiommusti,phy-type#thermal-sensor-cellsgpiosdefault-statelinux,default-triggerti,modelti,mcbspti,audio-routinglinux,codepowerdown-gpiosdigitalddc-i2c-busenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-active