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#address-cells#size-cellsmodelcompatiblestdout-pathgpio0gpio1serial0serial1device_typereginterrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesclocksstatuscache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerlinux,phandletimeout-msclock-frequencyreg-shiftreg-io-widthmarvell,pinsmarvell,functionngpiosgpio-controller#gpio-cells#clock-cellsmsi-controllerclock-namestx-csum-limitphyphy-modebuffer-managerbm,pool-longbm,pool-shortdmacap,memcpydmacap,xordmacap,memsetreg-namesmarvell,crypto-sramsmarvell,crypto-sram-sizeinternal-memclock-output-namesnum-csmarvell,nand-keep-configmarvell,nand-enable-arbiternand-on-flash-bbtnand-ecc-strengthnand-ecc-step-sizelabelmrvl,clk-delay-cyclesbroken-cdwp-invertedbus-widthno-1-8-vno-memory-wccell-indexspi-max-frequencymsi-parentbus-rangeassigned-addressesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-laneenable-method