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#address-cells#size-cellsmodelcompatiblestdout-pathgpio0gpio1serial0serial1device_typereginterrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesclocksstatuscache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerlinux,phandletimeout-mspinctrl-namespinctrl-0labelreg-shiftreg-io-widthmarvell,pinsmarvell,functionngpiosgpio-controller#gpio-cells#clock-cellsmsi-controllerclock-namestx-csum-limitphy-modespeedfull-duplexdmacap,memcpydmacap,xordmacap,memsetreg-namesmarvell,crypto-sramsmarvell,crypto-sram-sizeinternal-memclock-output-namesnum-csmarvell,nand-keep-configmarvell,nand-enable-arbiternand-on-flash-bbtread-onlymrvl,clk-delay-cyclesusb-phyno-memory-wccell-indexmsi-parentbus-rangeassigned-addressesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-laneclock-frequencyenable-methodvcc-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highgpiolinux,codedefault-statedsa,ethernetdsa,mii-bus