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:?¾Åokay„default’spi-flash@0!st,m25p128jedec,spi-nor`™7ù€pcie-controller!marvell,armada-370-pcieÅokayTpci«¶ÿP·‚ð ‚ð ‚@ð@ ‚€ð€ ‚è�à‚è�à‚Ø�Ђ¸�°pcie@1,0TpciÀ‚ `E@·‚‚��Ó æô¾ Åokaypcie@2,0TpciÀ‚ `E@·‚‚��Ó æ!ô¾ Åokaypcie@3,0TpciÀ‚@ `E@·‚‚��Ó æFô¾ Åokaypcie@4,0TpciÀ‚€ ` E@·‚‚��Ó æGô¾  Ådisabledclocksmainpll !fixed-clockô;šÊkqoscillator !fixed-clockô}x@kqcpus(marvell,armada-380-smpcpu@0Tcpu!arm,cortex-a9`cpu@1Tcpu!arm,cortex-a9`usb3_phy!usb-nop-xceiv6kqxhci0-vbus!regulator-fixed„default’ Axhci0-vbusPLK@hLK@€ “ kq #address-cells#size-cellsmodelcompatiblestdout-pathgpio0gpio1serial0serial1device_typereginterrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesclocksstatuscache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerlinux,phandletimeout-mspinctrl-namespinctrl-0reg-shiftreg-io-widthmarvell,pinsmarvell,functionngpiosgpio-controller#gpio-cells#clock-cellsmsi-controllerclock-namestx-csum-limitphyphy-modebuffer-managerbm,pool-longbm,pool-shortdmacap,memcpydmacap,xordmacap,memsetreg-namesmarvell,crypto-sramsmarvell,crypto-sram-sizeinternal-memclock-output-namesnum-csnand-ecc-strengthnand-ecc-step-sizemarvell,nand-keep-configmarvell,nand-enable-arbiternand-on-flash-bbtlabelread-onlymrvl,clk-delay-cyclesusb-phyno-memory-wccell-indexspi-max-frequencymsi-parentbus-rangeassigned-addressesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-laneclock-frequencyenable-methodvcc-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highgpio