Ð þí7Ê84¬(4t ,Xunlong Orange Pi Plus / Plus 2)2xunlong,orangepi-plusallwinner,sun8i-h3chosen=serial0:115200n8aliasesI/soc/serial@01c28000Q/soc/mmc@01c10000/sdio_wifi@1memory[memorygcpuscpu@02arm,cortex-a7[cpugcpu@12arm,cortex-a7[cpugcpu@22arm,cortex-a7[cpugcpu@32arm,cortex-a7[cpugtimer2arm,armv7-timer0k   clocksvosc24M_clk} 2fixed-clockŠn6šosc24M­³osc32k_clk} 2fixed-clockŠ€šosc32k­³apb0_clk2fixed-factor-clock}»ÅКapb0­³clk@01f01428@2allwinner,sun8i-h3-apb0-gates-clkallwinner,sun4i-a10-gates-clkgð(}Ðךapb0_pioapb0_ir­³ir_clk@01f014542allwinner,sun4i-a10-mod0-clkgðT}Кir­³soc 2simple-busvdma-controller@01c020002allwinner,sun8i-h3-dmagÀ  k2Ðåì­³mmc@01c0f0002allwinner,sun7i-a20-mmcgÀð ÐGIH÷ahbmmcoutputsampleåahb k<okaydefault$.:D Mmmc@01c100002allwinner,sun7i-a20-mmcgÁ ÐJLK÷ahbmmcoutputsampleåahb k=okaydefault$ .Y :dsdio_wifi@1gmmc@01c110002allwinner,sun7i-a20-mmcgÁ ÐMON÷ahbmmcoutputsampleå ahb k>okaydefault$ .:drphy@01c194002allwinner,sun8i-h3-usb-phy(gÁ”,Á¨Á¸ÁÈÁ؃phy_ctrlpmu0pmu1pmu2pmu3 ÐXYZ[$÷usb0_phyusb1_phyusb2_phyusb3_phy å,usb0_resetusb1_resetusb2_resetusb3_resetokay�˜ ©­³usb@01c1b000%2allwinner,sun8i-h3-ehcigeneric-ehcigÁ° kJÐ"&庿usbokayusb@01c1b400%2allwinner,sun8i-h3-ohcigeneric-ohcigÁ´ kKÐ"&]庿usb disabledusb@01c1c000%2allwinner,sun8i-h3-ehcigeneric-ehcigÁÀ kLÐ#'庿usb disabledusb@01c1c400%2allwinner,sun8i-h3-ohcigeneric-ohcigÁÄ kMÐ#'^庿usb disabledusb@01c1d000%2allwinner,sun8i-h3-ehcigeneric-ehcigÁÐ kNÐ$(庿usbokayusb@01c1d400%2allwinner,sun8i-h3-ohcigeneric-ohcigÁÔ kOÐ$(_庿usb disabledclock@01c200002allwinner,sun8i-h3-ccugÂÐ ÷hosclosc}É­³pinctrl@01c208002allwinner,sun8i-h3-pinctrlgÂk Ð6Öæò­ ³ i2c0 PA11PA12'i2c0:J­³i2c1 PA18PA19'i2c1:J­³i2c2 PE12PE13'i2c2:J­³mmc0@0PF0PF1PF2PF3PF4PF5'mmc0:J­³mmc0_cd_pin@0PF6'gpio_in:J­³mmc1@0PG0PG1PG2PG3PG4PG5'mmc1:J­ ³ mmc2_8bit3PC5PC6PC8PC9PC10PC11PC12PC13PC14PC15PC16'mmc2:J­ ³ uart0@0PA4PA5'uart0:J­³uart1PG6PG7'uart1:J­³uart1_rts_ctsPG8PG9'uart1:Juart2PA0PA1'uart2:J­³uart3 PA13PA14'uart3:J­³ahci_pwr_pin@0PB8 'gpio_out:J­³usb0_vbus_pin@0PB9 'gpio_out:J­³usb1_vbus_pin@0PG13 'gpio_out:J­³usb2_vbus_pin@0PH3 'gpio_out:J­³led_pins@0PA15 'gpio_out:J­ ³ usb3_vbus_pin@0PG11 'gpio_out:J­%³%timer@01c20c002allwinner,sun4i-a10-timerg  kÐwatchdog@01c20ca02allwinner,sun6i-a31-wdtg    kpwm@01c214002allwinner,sun8i-h3-pwmgÂÐY disabledserial@01c280002snps,dw-apb-uartg€ kdnÐ>å1{€rxtxokaydefault$serial@01c284002snps,dw-apb-uartg„ kdnÐ?å2{€rxtx disableddefault$serial@01c288002snps,dw-apb-uartgˆ kdnÐ@å3{€rxtx disableddefault$serial@01c28c002snps,dw-apb-uartgÂŒ kdnÐAå4{  €rxtx disableddefault$i2c@01c2ac002allwinner,sun6i-a31-i2cg¬ kÐ;å.default$ disabledi2c@01c2b0002allwinner,sun6i-a31-i2cg° kÐ<å/default$ disabledi2c@01c2b4002allwinner,sun6i-a31-i2cg° kÐ=å0default$ disabledinterrupt-controller@01c81000%2arm,cortex-a7-gicarm,cortex-a15-gic gÈÈ È@ È` ò k ­³rtc@01f000002allwinner,sun6i-a31-rtcgðTk()reset@01f014b0gð° 2allwinner,sun6i-a31-clock-resetÉ­³ir@01f020002allwinner,sun5i-a13-ir Ð÷apbirå k%gð @okaydefault$pinctrl@01f02c002allwinner,sun8i-h3-r-pinctrlgð, k-ÐåÖæò­"³"ir@0PL11 's_cir_rx:J­³led_pins@0PL10 'gpio_out:J­!³!key_pins@0PL3PL4'gpio_in:J­#³#wifi_pwrseq_pin@0PL7 'gpio_out:J­$³$ahci-5v2regulator-fixeddefault$Šahci-5v™LK@±LK@ÉÛî  disabledusb0-vbus2regulator-fixeddefault$ Šusb0-vbus™LK@±LK@Ûî   disabledusb1-vbus2regulator-fixeddefault$ Šusb1-vbus™LK@±LK@ÉÛî  okay­ ³ usb2-vbus2regulator-fixeddefault$ Šusb2-vbus™LK@±LK@ÉÛî  disabledvcc3v02regulator-fixedŠvcc3v0™-ÆÀ±-ÆÀvcc3v32regulator-fixedŠvcc3v3™2Z ±2Z ­³vcc5v02regulator-fixedŠvcc5v0™LK@±LK@leds 2gpio-ledsdefault$ !status_ledóorangepi:red:statusG pwr_ledóorangepi:green:pwrG" ùonr_gpio_keys 2gpio-keysdefault$#sw2ósw2G"sw4ósw4G"wifi_pwrseq2mmc-pwrseq-simpledefault$$"­ ³ usb3-vbus2regulator-fixeddefault$% Šusb3-vbus™LK@±LK@ÉÛî  ­³ #address-cells#size-cellsinterrupt-parentmodelcompatiblestdout-pathserial0ethernet1device_typereginterruptsranges#clock-cellsclock-frequencyclock-output-nameslinux,phandleclock-divclock-multclocksclock-indicesresets#dma-cellsclock-namesreset-namesstatuspinctrl-namespinctrl-0vmmc-supplybus-widthcd-gpioscd-invertedmmc-pwrseqnon-removablecap-mmc-hw-resetreg-names#phy-cellsusb1_vbus-supplyusb3_vbus-supplyphysphy-names#reset-cellsgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellsallwinner,pinsallwinner,functionallwinner,driveallwinner,pull#pwm-cellsreg-shiftreg-io-widthdmasdma-namesregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onenable-active-highgpiolabeldefault-statelinux,codereset-gpios