Ð þíGÙHCh(qC Terasic SoCkit#!altr,socfpga-cyclone5altr,socfpgachosen ,earlyprintk5serial0:115200n8aliasesA/soc/ethernet@ff702000K/soc/ethernet@ff702000U/soc/serial0@ffc02000]/soc/serial1@ffc03000e/soc/timer0@ffc08000l/soc/timer1@ffc09000s/soc/timer2@ffd00000z/soc/timer3@ffd01000memory�memory�@cpus‘altr,socfpga-smpcpu@0!arm,cortex-a9�cpu�Ÿcpu@1!arm,cortex-a9�cpu�Ÿintc@fffed000!arm,cortex-a9-gic°Á�ÿþÐÿþÁÖÜsoc !simple-bus�socäõamba !simple-busõpdma@ffe01000!arm,pl330arm,primecell�ÿà`ühijklmno . 5apb_pclkÖ+Ü+can@ffc00000 !bosch,d_can�ÿÀ0üƒ„…†. Adisabledcan@ffc01000 !bosch,d_can�ÿÀ0ü‡ˆ‰Š. Adisabledclkmgr@ffd04000 !altr,clk-mgr�ÿÐ@clocksosc1H !fixed-clockU}x@ÖÜosc2H !fixed-clockÖÜf2s_periph_ref_clkH !fixed-clockÖ Ü f2s_sdram_ref_clkH !fixed-clockÖ Ü main_pllH!altr,socfpga-pll-clock.�@ÖÜmpuclkH!altr,socfpga-perip-clk. eà �HÖ Ü mainclkH!altr,socfpga-perip-clk. eä �LÖÜdbg_base_clkH!altr,socfpga-perip-clk. eè �PÖÜmain_qspi_clkH!altr,socfpga-perip-clk.�TÖÜmain_nand_sdmmc_clkH!altr,socfpga-perip-clk.�XÖÜcfg_h2f_usr0_clkH!altr,socfpga-perip-clk.�\ÖÜperiph_pllH!altr,socfpga-pll-clock . �€Ö Ü emac0_clkH!altr,socfpga-perip-clk. �ˆÖÜemac1_clkH!altr,socfpga-perip-clk. �ŒÖÜper_qsi_clkH!altr,socfpga-perip-clk. ��ÖÜper_nand_mmc_clkH!altr,socfpga-perip-clk. �”ÖÜper_base_clkH!altr,socfpga-perip-clk. �˜ÖÜh2f_usr1_clkH!altr,socfpga-perip-clk. �œÖÜsdram_pllH!altr,socfpga-pll-clock . �ÀÖ Ü ddr_dqs_clkH!altr,socfpga-perip-clk. �ÈÖÜddr_2x_dqs_clkH!altr,socfpga-perip-clk. �ÌÖÜddr_dq_clkH!altr,socfpga-perip-clk. �ÐÖÜh2f_usr2_clkH!altr,socfpga-perip-clk. �ÔÖÜmpu_periph_clkH!altr,socfpga-perip-clk. mÖ*Ü*mpu_l2_ram_clkH!altr,socfpga-perip-clk. ml4_main_clkH!altr,socfpga-gate-clk.{`ÖÜl3_main_clkH!altr,socfpga-perip-clk.ml3_mp_clkH!altr,socfpga-gate-clk. ed{`ÖÜl3_sp_clkH!altr,socfpga-gate-clk. edl4_mp_clkH!altr,socfpga-gate-clk. ed{`Ö"Ü"l4_sp_clkH!altr,socfpga-gate-clk. ed{`Ö#Ü#dbg_at_clkH!altr,socfpga-gate-clk. eh{`ÖÜdbg_clkH!altr,socfpga-gate-clk. eh{`dbg_trace_clkH!altr,socfpga-gate-clk. el{`dbg_timer_clkH!altr,socfpga-gate-clk.{`cfg_clkH!altr,socfpga-gate-clk.{`h2f_user0_clkH!altr,socfpga-gate-clk.{` emac_0_clkH!altr,socfpga-gate-clk.{ emac_1_clkH!altr,socfpga-gate-clk.{ usb_mp_clkH!altr,socfpga-gate-clk.{  e¤Ö,Ü,spi_m_clkH!altr,socfpga-gate-clk.{  e¤Ö)Ü)can0_clkH!altr,socfpga-gate-clk.{  e¤ÖÜcan1_clkH!altr,socfpga-gate-clk.{  e¤ ÖÜgpio_db_clkH!altr,socfpga-gate-clk.{  e¨h2f_user1_clkH!altr,socfpga-gate-clk.{ sdmmc_clkH!altr,socfpga-gate-clk . { „‡ÖÜsdmmc_clk_dividedH!altr,socfpga-gate-clk.{ mÖ&Ü&nand_x_clkH!altr,socfpga-gate-clk . {  nand_clkH!altr,socfpga-gate-clk . {  mqspi_clkH!altr,socfpga-gate-clk . {  ddr_dqs_clk_gateH!altr,socfpga-gate-clk.{Øddr_2x_dqs_clk_gateH!altr,socfpga-gate-clk.{Øddr_dq_clk_gateH!altr,socfpga-gate-clk.{Øh2f_user2_clkH!altr,socfpga-gate-clk.{Øfpgamgr@ff706000!altr,socfpga-fpga-mgr�ÿp`ÿ¹ ü¯ethernet@ff7000000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac Ž `�ÿp  üs¡macirq±. 5stmmaceth½!  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Adisabledleds !gpio-ledshps_led0úhps:blue:led0 ¶. heartbeathps_led1úhps:blue:led1 ¶. heartbeathps_led2úhps:blue:led2 ¶. heartbeathps_led3úhps:blue:led3 ¶. heartbeatgpio-keys !gpio-keyshps_sw0úhps_sw0 ¶$'hps_sw1úhps_sw1 ¶$'hps_sw2úhps_sw2 ¶$' hps_sw3úhps_sw3 ¶$' hps_hkey0 úhps_hkey0 ¶$'»hps_hkey1 úhps_hkey1 ¶$'¼hps_hkey2 úhps_hkey2 ¶$'½hps_hkey3 úhps_hkey3 ¶$'¾vcc3p3-regulator!regulator-fixed2VCC3P3A2Z Y2Z Ö'Ü' #address-cells#size-cellsmodelcompatiblebootargsstdout-pathethernet0ethernet1serial0serial1timer0timer1timer2timer3device_typeregenable-methodnext-level-cache#interrupt-cellsinterrupt-controllerlinux,phandleinterrupt-parentrangesinterrupts#dma-cells#dma-channels#dma-requestsclocksclock-namesstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phasealtr,sysmgr-sysconinterrupt-namesmac-addressresetsreset-namessnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthphy-moderxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-psgpio-controller#gpio-cellssnps,nr-gpiosiramcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrnum-slotsbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedvmmc-supplyvqmmc-supply#reset-cellsaltr,modrst-offsetaltr,sdr-sysconnum-cscpu1-start-addrreg-shiftreg-io-widthdmasdma-names#phy-cellsphysphy-nameslabellinux,default-triggerlinux,input-typelinux,coderegulator-nameregulator-min-microvoltregulator-max-microvolt