Ð þí/ï8,,(Ã+ô!,Rockchip RK3228 Evaluation board$2rockchip,rk3228-evbrockchip,rk3228chosenaliases=/serial@11010000E/serial@11020000M/serial@11030000memoryUmemorya`@cpuscpu@f00Ucpu2arm,cortex-a7ael s€B@}Œœ@š¡§cpu@f01Ucpu2arm,cortex-a7ae¡§cpu@f02Ucpu2arm,cortex-a7ae¡§cpu@f03Ucpu2arm,cortex-a7ae¡§amba 2simple-bus¯pdma@110f00002arm,pl330arm,primecella@¶ÁšÂ Ìapb_pclk¡§arm-pmu2arm,cortex-a7-pmu0¶LMNOØtimer2arm,armv7-timerë0¶   n6oscillator 2fixed-clockn6xin24m2¡§i2s1@100b0000(2rockchip,rk3228-i2srockchip,rk3066-i2sa @ ¶Ìi2s_clki2s_hclkšQ»?DtxrxNdefault\ fdisabledi2s0@100c0000(2rockchip,rk3228-i2srockchip,rk3066-i2sa @ ¶Ìi2s_clki2s_hclkšPº?  Dtxrx fdisabledi2s2@100e0000(2rockchip,rk3228-i2srockchip,rk3066-i2sa@ ¶Ìi2s_clki2s_hclkšR¼?Dtxrx fdisabledsyscon@110000002syscona¡§serial@110100002snps,dw-apb-uarta ¶7n6šMUÌbaudclkapb_pclkNdefault \ mw fdisabledserial@110200002snps,dw-apb-uarta ¶8n6šNVÌbaudclkapb_pclkNdefault\ mw fdisabledserial@110300002snps,dw-apb-uarta ¶9n6šOWÌbaudclkapb_pclkNdefault\ mwfokayi2c@110500002rockchip,rk3228-i2ca ¶$Ìi2cšLNdefault\ fdisabledi2c@110600002rockchip,rk3228-i2ca ¶%Ìi2cšMNdefault\ fdisabledi2c@110700002rockchip,rk3228-i2ca ¶&Ìi2cšNNdefault\ fdisabledi2c@110800002rockchip,rk3228-i2ca ¶'Ìi2cšONdefault\ fdisabledpwm@110b00002rockchip,rk3288-pwma „š^ÌpwmNdefault\ fdisabledpwm@110b00102rockchip,rk3288-pwma „š^ÌpwmNdefault\ fdisabledpwm@110b00202rockchip,rk3288-pwma „š^ÌpwmNdefault\ fdisabledpwm@110b00302rockchip,rk3288-pwma 0„š^ÌpwmNdefault\ fdisabledtimer@110c00002rockchip,rk3288-timera  ¶+ ša Ìtimerpclkclock-controller@110e00002rockchip,rk3228-crua�2œ©¹#g¸€¡§thermal-zonescpu-thermalÎdäˆòtripscpu_alert0pÐ\passive¡§cpu_alert1$øÐ\passive¡§cpu_crit_�Ð \criticalcooling-mapsmap0 ÿÿÿÿmap1 ÿÿÿÿÿÿÿÿtsadc@111500002rockchip,rk3228-tsadca ¶:šHXÌtsadcapb_pclkeW -tsadc-apbNinitdefaultsleep\9CMcsfokayz‘¡§dwmmc@300200002rockchip,rk3288-dw-mshca0@ ¶<4`¬€<4` šËGuyÌbiuciuciu_drvciu_sample¿ÉžÞèNdefault \fokayóethernet@302000002rockchip,rk3228-gmaca0  ¶+macirq8š~�‚€ÔoMÌstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mace8 -stmmaceth� fdisabledinterrupt-controller@32010000 2arm,gic-400;P a22 2@ 2`  ¶ ¡§pinctrl2rockchip,rk3228-pinctrl�¯gpio0@111100002rockchip,gpio-banka ¶3š@aq;Pgpio1@111200002rockchip,gpio-banka ¶4šAaq;Pgpio2@111300002rockchip,gpio-banka ¶5šBaq;Pgpio3@111400002rockchip,gpio-banka ¶6šCaq;Ppcfg-pull-up}pcfg-pull-downŠpcfg-pull-none™¡ § pcfg-pull-none-drv-12ma¦ ¡!§!emmcemmc-clkµ ¡§emmc-cmdµ ¡§emmc-bus8€µ        ¡§gmacrgmii-pinsðµ    !!!! ! !       rmii-pins µ    !! !    phy-pins µ  i2c0i2c0-xfer µ  ¡§i2c1i2c1-xfer µ  ¡§i2c2i2c2-xfer µ  ¡§i2c3i2c3-xfer µ  ¡§i2s1i2s1-bus�µ         ¡§pwm0pwm0-pinµ ¡§pwm1pwm1-pinµ ¡§pwm2pwm2-pinµ  ¡§pwm3pwm3-pinµ  ¡§tsadcotp-gpioµ ¡§otp-outµ ¡§uart0uart0-xfer µ  ¡ § uart0-ctsµ ¡ § uart0-rtsµ ¡ § uart1uart1-xfer µ    ¡ § uart1-ctsµ uart1-rtsµ  uart2uart2-xfer µ  ¡ § uart2-ctsµ uart2-rtsµ  #address-cells#size-cellsinterrupt-parentmodelcompatibleserial0serial1serial2device_typeregresetsoperating-points#cooling-cellsclock-latencyclockslinux,phandlerangesinterrupts#dma-cellsclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsdmasdma-namespinctrl-namespinctrl-0statusreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityclock-freq-min-maxbus-widthdefault-sample-phasenum-slotsfifo-depthcap-mmc-highspeedmmc-ddr-1_8vdisable-wpnon-removableinterrupt-namesinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pins