Ð þíûc8ô (CóèEheadacoustics,omap3-hatechnexion,omap3-tao3530ti,omap34xxti,omap3 +37TI OMAP3 HEAD acoustics baseboard with TAO3530 SOMaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000cpus+cpu@0arm,cortex-a8dcpupt{cpu‡“à(•èHà˜Ð�g8¡ O€dp`ð 'À™p¦pmu@54000000arm,cortex-a8-pmupT€²½debugsssocti,omap-inframpu ti,omap3-mpu½mpuiva ti,iva2.2½ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busph² +ǽl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ ÇHscm@2000ti,omap3-scmsimple-busp + Ç pinmux@30 ti,omap3-padconfpinctrl-singlep08+Îßôÿ/default= pinmux_hsusbb2_pins`GÀÂÄ Æ È Ê ¤ ¦ ¨ ª ¬ ® [apinmux_mmc1_pinsPG "$&[ôaôpinmux_mmc2_pins0G(*,.02[øaøpinmux_wlan_gpioG^pinmux_uart3_pinsGnAp[êaêpinmux_i2c3_pinsG’”[ðaðpinmux_mcspi1_pins G˜šœž[ñañpinmux_mcspi3_pins G¬®°²[òaòpinmux_mcbsp3_pins G<>@B[ýaýpinmux_twl4030_pinsG°A[ëaëpinmux_sound2_pinsGnpinmux_led_blue_pinsGà[apinmux_led_green_pinsGö[ a pinmux_led_red_pinsGþ[ a pinmux_poweroff_pinsGŽ[ a pinmux_powerdown_input_pinsG�[afpga_boot0_pins Gêìîð[afpga_boot1_pins Grtvx[ascm_conf@270sysconsimple-buspp0+ Çp0[ a pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapp°i pbias_mmc_omap2430ppbias_mmc_omap2430w@—-ÆÀ[óaóclocks+mcbsp5_mux_fck@68¯ti,composite-mux-clockt ¼ph[amcbsp5_fck¯ti,composite-clockt[ÿaÿmcbsp1_mux_fck@4¯ti,composite-mux-clockt ¼p[amcbsp1_fck¯ti,composite-clockt[úaúmcbsp2_mux_fck@4¯ti,composite-mux-clockt ¼p[amcbsp2_fck¯ti,composite-clockt[ûaûmcbsp3_mux_fck@68¯ti,composite-mux-clockt ph[amcbsp3_fck¯ti,composite-clockt[üaümcbsp4_mux_fck@68¯ti,composite-mux-clockt ¼ph[amcbsp4_fck¯ti,composite-clockt[þaþclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlep \+Îßôÿpinmux_twl4030_vpins G[ìaìaes@480c5000 ti,omap3-aes½aespH PP²ÉABÎtxrx Ødisabledprm@48306000 ti,omap3-prmpH0`@² clocks+virt_16_8m_ck¯ fixed-clockßY[aosc_sys_ck@d40¯ ti,mux-clocktp @[ a sys_ck@1270¯ti,divider-clockt ¼ïppú[%a%sys_clkout1@d70¯ti,gate-clockt p p¼dpll3_x2_ck¯fixed-factor-clockt!dpll3_m2x2_ck¯fixed-factor-clockt"[$a$dpll4_x2_ck¯fixed-factor-clockt#corex2_fck¯fixed-factor-clockt$[&a&wkup_l4_ick¯fixed-factor-clockt%[UaUcorex2_d3_fck¯fixed-factor-clockt&[ŒaŒcorex2_d5_fck¯fixed-factor-clockt&[�a�clockdomainscm@48004000 ti,omap3-cmpH@@clocks+dummy_apb_pclk¯ fixed-clockßomap_32k_fck¯ fixed-clock߀[GaGvirt_12m_ck¯ fixed-clockß·[avirt_13m_ck¯ fixed-clock߯]@[avirt_19200000_ck¯ fixed-clockß$ø[avirt_26000000_ck¯ fixed-clockߌº€[avirt_38_4m_ck¯ fixed-clockßIð[adpll4_ck@d00¯ti,omap3-dpll-per-clockt%%p D 0[#a#dpll4_m2_ck@d48¯ti,divider-clockt#ï?p Hú['a'dpll4_m2x2_mul_ck¯fixed-factor-clockt'[(a(dpll4_m2x2_ck@d00¯ti,gate-clockt(¼p &[)a)omap_96m_alwon_fck¯fixed-factor-clockt)[0a0dpll3_ck@d00¯ti,omap3-dpll-core-clockt%%p @ 0[!a!dpll3_m3_ck@1140¯ti,divider-clockt!¼ïp@ú[*a*dpll3_m3x2_mul_ck¯fixed-factor-clockt*[+a+dpll3_m3x2_ck@d00¯ti,gate-clockt+¼ p &[,a,emu_core_alwon_ck¯fixed-factor-clockt,[iaisys_altclk¯ fixed-clockß[5a5mcbsp_clks¯ fixed-clockß[ a dpll3_m2_ck@d40¯ti,divider-clockt!¼ïp @ú["a"core_ck¯fixed-factor-clockt"[-a-dpll1_fck@940¯ti,divider-clockt-¼ïp @ú[.a.dpll1_ck@904¯ti,omap3-dpll-clockt%.p  $ @ 4[adpll1_x2_ck¯fixed-factor-clockt[/a/dpll1_x2m2_ck@944¯ti,divider-clockt/ïp Dú[CaCcm_96m_fck¯fixed-factor-clockt0[1a1omap_96m_fck@d40¯ ti,mux-clockt1%¼p @[LaLdpll4_m3_ck@e40¯ti,divider-clockt#¼ï p@ú[2a2dpll4_m3x2_mul_ck¯fixed-factor-clockt2[3a3dpll4_m3x2_ck@d00¯ti,gate-clockt3¼p &[4a4omap_54m_fck@d40¯ ti,mux-clockt45¼p @[?a?cm_96m_d2_fck¯fixed-factor-clockt1[6a6omap_48m_fck@d40¯ ti,mux-clockt65¼p @[7a7omap_12m_fck¯fixed-factor-clockt7[NaNdpll4_m4_ck@e40¯ti,divider-clockt#ï p@ú[8a8dpll4_m4x2_mul_ck¯ti,fixed-factor-clockt8<JW[9a9dpll4_m4x2_ck@d00¯ti,gate-clockt9¼p &W[�a�dpll4_m5_ck@f40¯ti,divider-clockt#ï?p@ú[:a:dpll4_m5x2_mul_ck¯ti,fixed-factor-clockt:<JW[;a;dpll4_m5x2_ck@d00¯ti,gate-clockt;¼p &W[qaqdpll4_m6_ck@1140¯ti,divider-clockt#¼ï?p@ú[<a<dpll4_m6x2_mul_ck¯fixed-factor-clockt<[=a=dpll4_m6x2_ck@d00¯ti,gate-clockt=¼p &[>a>emu_per_alwon_ck¯fixed-factor-clockt>[jajclkout2_src_gate_ck@d70¯ ti,composite-no-wait-gate-clockt-¼p p[@a@clkout2_src_mux_ck@d70¯ti,composite-mux-clockt-%1?p p[AaAclkout2_src_ck¯ti,composite-clockt@A[BaBsys_clkout2@d70¯ti,divider-clocktB¼ï@p pjmpu_ck¯fixed-factor-clocktC[DaDarm_fck@924¯ti,divider-clocktDp $ïemu_mpu_alwon_ck¯fixed-factor-clocktD[kakl3_ick@a40¯ti,divider-clockt-ïp @ú[EaEl4_ick@a40¯ti,divider-clocktE¼ïp @ú[FaFrm_ick@c40¯ti,divider-clocktF¼ïp @úgpt10_gate_fck@a00¯ti,composite-gate-clockt%¼ p [HaHgpt10_mux_fck@a40¯ti,composite-mux-clocktG%¼p @[IaIgpt10_fck¯ti,composite-clocktHIgpt11_gate_fck@a00¯ti,composite-gate-clockt%¼ p [JaJgpt11_mux_fck@a40¯ti,composite-mux-clocktG%¼p @[KaKgpt11_fck¯ti,composite-clocktJKcore_96m_fck¯fixed-factor-clocktL[ a mmchs2_fck@a00¯ti,wait-gate-clockt p ¼[»a»mmchs1_fck@a00¯ti,wait-gate-clockt p ¼[¼a¼i2c3_fck@a00¯ti,wait-gate-clockt p ¼[½a½i2c2_fck@a00¯ti,wait-gate-clockt p ¼[¾a¾i2c1_fck@a00¯ti,wait-gate-clockt p ¼[¿a¿mcbsp5_gate_fck@a00¯ti,composite-gate-clockt ¼ p [amcbsp1_gate_fck@a00¯ti,composite-gate-clockt ¼ p [acore_48m_fck¯fixed-factor-clockt7[MaMmcspi4_fck@a00¯ti,wait-gate-clocktMp ¼[ÀaÀmcspi3_fck@a00¯ti,wait-gate-clocktMp ¼[ÁaÁmcspi2_fck@a00¯ti,wait-gate-clocktMp ¼[ÂaÂmcspi1_fck@a00¯ti,wait-gate-clocktMp ¼[ÃaÃuart2_fck@a00¯ti,wait-gate-clocktMp ¼[ÄaÄuart1_fck@a00¯ti,wait-gate-clocktMp ¼ [ÅaÅcore_12m_fck¯fixed-factor-clocktN[OaOhdq_fck@a00¯ti,wait-gate-clocktOp ¼[ÆaÆcore_l3_ick¯fixed-factor-clocktE[PaPsdrc_ick@a10¯ti,wait-gate-clocktPp ¼[‘a‘gpmc_fck¯fixed-factor-clocktPcore_l4_ick¯fixed-factor-clocktF[QaQmmchs2_ick@a10¯ti,omap3-interface-clocktQp ¼[ÇaÇmmchs1_ick@a10¯ti,omap3-interface-clocktQp ¼[ÈaÈhdq_ick@a10¯ti,omap3-interface-clocktQp ¼[ÉaÉmcspi4_ick@a10¯ti,omap3-interface-clocktQp ¼[ÊaÊmcspi3_ick@a10¯ti,omap3-interface-clocktQp ¼[ËaËmcspi2_ick@a10¯ti,omap3-interface-clocktQp ¼[ÌaÌmcspi1_ick@a10¯ti,omap3-interface-clocktQp ¼[ÍaÍi2c3_ick@a10¯ti,omap3-interface-clocktQp ¼[ÎaÎi2c2_ick@a10¯ti,omap3-interface-clocktQp ¼[ÏaÏi2c1_ick@a10¯ti,omap3-interface-clocktQp ¼[ÐaÐuart2_ick@a10¯ti,omap3-interface-clocktQp ¼[ÑaÑuart1_ick@a10¯ti,omap3-interface-clocktQp ¼ [ÒaÒgpt11_ick@a10¯ti,omap3-interface-clocktQp ¼ [ÓaÓgpt10_ick@a10¯ti,omap3-interface-clocktQp ¼ [ÔaÔmcbsp5_ick@a10¯ti,omap3-interface-clocktQp ¼ [ÕaÕmcbsp1_ick@a10¯ti,omap3-interface-clocktQp ¼ [ÖaÖomapctrl_ick@a10¯ti,omap3-interface-clocktQp ¼[×a×dss_tv_fck@e00¯ti,gate-clockt?p¼[¶a¶dss_96m_fck@e00¯ti,gate-clocktLp¼[·a·dss2_alwon_fck@e00¯ti,gate-clockt%p¼[¸a¸dummy_ck¯ fixed-clockßgpt1_gate_fck@c00¯ti,composite-gate-clockt%¼p [RaRgpt1_mux_fck@c40¯ti,composite-mux-clocktG%p @[SaSgpt1_fck¯ti,composite-clocktRSaes2_ick@a10¯ti,omap3-interface-clocktQ¼p [ØaØwkup_32k_fck¯fixed-factor-clocktG[TaTgpio1_dbck@c00¯ti,gate-clocktTp ¼[­a­sha12_ick@a10¯ti,omap3-interface-clocktQp ¼[ÙaÙwdt2_fck@c00¯ti,wait-gate-clocktTp ¼[®a®wdt2_ick@c10¯ti,omap3-interface-clocktUp ¼[¯a¯wdt1_ick@c10¯ti,omap3-interface-clocktUp ¼[°a°gpio1_ick@c10¯ti,omap3-interface-clocktUp ¼[±a±omap_32ksync_ick@c10¯ti,omap3-interface-clocktUp ¼[²a²gpt12_ick@c10¯ti,omap3-interface-clocktUp ¼[³a³gpt1_ick@c10¯ti,omap3-interface-clocktUp ¼[´a´per_96m_fck¯fixed-factor-clockt0[aper_48m_fck¯fixed-factor-clockt7[VaVuart3_fck@1000¯ti,wait-gate-clocktVp¼ [“a“gpt2_gate_fck@1000¯ti,composite-gate-clockt%¼p[WaWgpt2_mux_fck@1040¯ti,composite-mux-clocktG%p@[XaXgpt2_fck¯ti,composite-clocktWXgpt3_gate_fck@1000¯ti,composite-gate-clockt%¼p[YaYgpt3_mux_fck@1040¯ti,composite-mux-clocktG%¼p@[ZaZgpt3_fck¯ti,composite-clocktYZgpt4_gate_fck@1000¯ti,composite-gate-clockt%¼p[[a[gpt4_mux_fck@1040¯ti,composite-mux-clocktG%¼p@[\a\gpt4_fck¯ti,composite-clockt[\gpt5_gate_fck@1000¯ti,composite-gate-clockt%¼p[]a]gpt5_mux_fck@1040¯ti,composite-mux-clocktG%¼p@[^a^gpt5_fck¯ti,composite-clockt]^gpt6_gate_fck@1000¯ti,composite-gate-clockt%¼p[_a_gpt6_mux_fck@1040¯ti,composite-mux-clocktG%¼p@[`a`gpt6_fck¯ti,composite-clockt_`gpt7_gate_fck@1000¯ti,composite-gate-clockt%¼p[aaagpt7_mux_fck@1040¯ti,composite-mux-clocktG%¼p@[babgpt7_fck¯ti,composite-clocktabgpt8_gate_fck@1000¯ti,composite-gate-clockt%¼ p[cacgpt8_mux_fck@1040¯ti,composite-mux-clocktG%¼p@[dadgpt8_fck¯ti,composite-clocktcdgpt9_gate_fck@1000¯ti,composite-gate-clockt%¼ p[eaegpt9_mux_fck@1040¯ti,composite-mux-clocktG%¼p@[fafgpt9_fck¯ti,composite-clocktefper_32k_alwon_fck¯fixed-factor-clocktG[gaggpio6_dbck@1000¯ti,gate-clocktgp¼[”a”gpio5_dbck@1000¯ti,gate-clocktgp¼[•a•gpio4_dbck@1000¯ti,gate-clocktgp¼[–a–gpio3_dbck@1000¯ti,gate-clocktgp¼[—a—gpio2_dbck@1000¯ti,gate-clocktgp¼ [˜a˜wdt3_fck@1000¯ti,wait-gate-clocktgp¼ [™a™per_l4_ick¯fixed-factor-clocktF[hahgpio6_ick@1010¯ti,omap3-interface-clockthp¼[šašgpio5_ick@1010¯ti,omap3-interface-clockthp¼[›a›gpio4_ick@1010¯ti,omap3-interface-clockthp¼[œaœgpio3_ick@1010¯ti,omap3-interface-clockthp¼[�a�gpio2_ick@1010¯ti,omap3-interface-clockthp¼ [žažwdt3_ick@1010¯ti,omap3-interface-clockthp¼ [ŸaŸuart3_ick@1010¯ti,omap3-interface-clockthp¼ [ a uart4_ick@1010¯ti,omap3-interface-clockthp¼[¡a¡gpt9_ick@1010¯ti,omap3-interface-clockthp¼ [¢a¢gpt8_ick@1010¯ti,omap3-interface-clockthp¼ [£a£gpt7_ick@1010¯ti,omap3-interface-clockthp¼[¤a¤gpt6_ick@1010¯ti,omap3-interface-clockthp¼[¥a¥gpt5_ick@1010¯ti,omap3-interface-clockthp¼[¦a¦gpt4_ick@1010¯ti,omap3-interface-clockthp¼[§a§gpt3_ick@1010¯ti,omap3-interface-clockthp¼[¨a¨gpt2_ick@1010¯ti,omap3-interface-clockthp¼[©a©mcbsp2_ick@1010¯ti,omap3-interface-clockthp¼[ªaªmcbsp3_ick@1010¯ti,omap3-interface-clockthp¼[«a«mcbsp4_ick@1010¯ti,omap3-interface-clockthp¼[¬a¬mcbsp2_gate_fck@1000¯ti,composite-gate-clockt ¼p[amcbsp3_gate_fck@1000¯ti,composite-gate-clockt ¼p[amcbsp4_gate_fck@1000¯ti,composite-gate-clockt ¼p[aemu_src_mux_ck@1140¯ ti,mux-clockt%ijkp@[lalemu_src_ck¯ti,clkdm-gate-clocktl[mampclk_fck@1140¯ti,divider-clocktm¼ïp@úpclkx2_fck@1140¯ti,divider-clocktm¼ïp@úatclk_fck@1140¯ti,divider-clocktm¼ïp@útraceclk_src_fck@1140¯ ti,mux-clockt%ijk¼p@[nantraceclk_fck@1140¯ti,divider-clocktn¼ ïp@úsecure_32k_fck¯ fixed-clock߀[oaogpt12_fck¯fixed-factor-clocktowdt1_fck¯fixed-factor-clocktosecurity_l4_ick2¯fixed-factor-clocktF[papaes1_ick@a14¯ti,omap3-interface-clocktp¼p rng_ick@a14¯ti,omap3-interface-clocktpp ¼sha11_ick@a14¯ti,omap3-interface-clocktpp ¼des1_ick@a14¯ti,omap3-interface-clocktpp ¼cam_mclk@f00¯ti,gate-clocktq¼pWcam_ick@f10¯!ti,omap3-no-wait-interface-clocktFp¼[àaàcsi2_96m_fck@f00¯ti,gate-clockt p¼[áaásecurity_l3_ick¯fixed-factor-clocktE[rarpka_ick@a14¯ti,omap3-interface-clocktrp ¼icr_ick@a10¯ti,omap3-interface-clocktQp ¼des2_ick@a10¯ti,omap3-interface-clocktQp ¼mspro_ick@a10¯ti,omap3-interface-clocktQp ¼mailboxes_ick@a10¯ti,omap3-interface-clocktQp ¼ssi_l4_ick¯fixed-factor-clocktF[yaysr1_fck@c00¯ti,wait-gate-clockt%p ¼sr2_fck@c00¯ti,wait-gate-clockt%p ¼sr_l4_ick¯fixed-factor-clocktFdpll2_fck@40¯ti,divider-clockt-¼ïp@ú[sasdpll2_ck@4¯ti,omap3-dpll-clockt%sp$@4€’š[tatdpll2_m2_ck@44¯ti,divider-clockttïpDú[uauiva2_ck@0¯ti,wait-gate-clocktup¼[âaâmodem_fck@a00¯ti,omap3-interface-clockt%p ¼[ãaãsad2d_ick@a10¯ti,omap3-interface-clocktEp ¼[äaämad2d_ick@a18¯ti,omap3-interface-clocktEp ¼[åaåmspro_fck@a00¯ti,wait-gate-clockt p ¼ssi_ssr_gate_fck_3430es2@a00¯ ti,composite-no-wait-gate-clockt&¼p [vavssi_ssr_div_fck_3430es2@a40¯ti,composite-divider-clockt&¼p @$®[wawssi_ssr_fck_3430es2¯ti,composite-clocktvw[xaxssi_sst_fck_3430es2¯fixed-factor-clocktx[ahsotgusb_ick_3430es2@a10¯"ti,omap3-hsotgusb-interface-clocktPp ¼[’a’ssi_ick_3430es2@a10¯ti,omap3-ssi-interface-clocktyp ¼[ausim_gate_fck@c00¯ti,composite-gate-clocktL¼ p [„a„sys_d2_ck¯fixed-factor-clockt%[{a{omap_96m_d2_fck¯fixed-factor-clocktL[|a|omap_96m_d4_fck¯fixed-factor-clocktL[}a}omap_96m_d8_fck¯fixed-factor-clocktL[~a~omap_96m_d10_fck¯fixed-factor-clocktL [adpll5_m2_d4_ck¯fixed-factor-clocktz[€a€dpll5_m2_d8_ck¯fixed-factor-clocktz[�a�dpll5_m2_d16_ck¯fixed-factor-clocktz[‚a‚dpll5_m2_d20_ck¯fixed-factor-clocktz[ƒaƒusim_mux_fck@c40¯ti,composite-mux-clock(t%{|}~€�‚ƒ¼p @ú[…a…usim_fck¯ti,composite-clockt„…usim_ick@c10¯ti,omap3-interface-clocktUp ¼ [µaµdpll5_ck@d04¯ti,omap3-dpll-clockt%%p  $ L 4€’[†a†dpll5_m2_ck@d50¯ti,divider-clockt†ïp Pú[zazsgx_gate_fck@b00¯ti,composite-gate-clockt-¼p [ŽaŽcore_d3_ck¯fixed-factor-clockt-[‡a‡core_d4_ck¯fixed-factor-clockt-[ˆaˆcore_d6_ck¯fixed-factor-clockt-[‰a‰omap_192m_alwon_fck¯fixed-factor-clockt)[ŠaŠcore_d2_ck¯fixed-factor-clockt-[‹a‹sgx_mux_fck@b40¯ti,composite-mux-clock t‡ˆ‰1Š‹Œ�p @[�a�sgx_fck¯ti,composite-clocktŽ�sgx_ick@b10¯ti,wait-gate-clocktEp ¼[æaæcpefuse_fck@a08¯ti,gate-clockt%p ¼[ÚaÚts_fck@a08¯ti,gate-clocktGp ¼[ÛaÛusbtll_fck@a08¯ti,wait-gate-clocktzp ¼[ÜaÜusbtll_ick@a18¯ti,omap3-interface-clocktQp ¼[ÝaÝmmchs3_ick@a10¯ti,omap3-interface-clocktQp ¼[ÞaÞmmchs3_fck@a00¯ti,wait-gate-clockt p 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