Ð þíúg8ò ([ñÔ timll,omap3-devkit8000ti,omap3 +7TimLL OMAP3 Devkit8000aliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/connector0 m/connector1cpus+cpu@0arm,cortex-a8vcpu‚†�cpu™“à(§èHà˜Ð�g8¡ O€dp`ð 'À™ppmu@54000000arm,cortex-a8-pmu‚T€¸Ãdebugsssocti,omap-inframpu ti,omap3-mpuÃmpuiva ti,iva2.2Ãivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus‚h¸ +ÍÃl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ ÍHscm@2000ti,omap3-scmsimple-bus‚ + Í pinmux@30 ti,omap3-padconfpinctrl-single‚08+Ôåúÿpinmux_twl4030_pins5°AIâOâpinmux_dss_dpi_pinsà5¤¦¨ª¬®°²´¶¸º¼¾ÀÂÄÆÈÊÌÎÐÒÔÖØÚIñOñscm_conf@270sysconsimple-bus‚p0+ Íp0IOpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap‚°Wpbias_mmc_omap2430^pbias_mmc_omap2430mw@…-ÆÀIçOçclocks+mcbsp5_mux_fck@68�ti,composite-mux-clock†ª‚hIOmcbsp5_fck�ti,composite-clock†IîOîmcbsp1_mux_fck@4�ti,composite-mux-clock†ª‚I O mcbsp1_fck�ti,composite-clock† IêOêmcbsp2_mux_fck@4�ti,composite-mux-clock† ª‚I O mcbsp2_fck�ti,composite-clock† IëOëmcbsp3_mux_fck@68�ti,composite-mux-clock† ‚hIOmcbsp3_fck�ti,composite-clock† IìOìmcbsp4_mux_fck@68�ti,composite-mux-clock† ª‚hIOmcbsp4_fck�ti,composite-clock†IíOíclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single‚ \+Ôåúÿpinmux_twl4030_vpins 5IãOãaes@480c5000 ti,omap3-aesÃaes‚H PP¸·AB¼txrxprm@48306000 ti,omap3-prm‚H0`@¸ clocks+virt_16_8m_ck� fixed-clockÆYIOosc_sys_ck@d40� ti,mux-clock†‚ @IOsys_ck@1270�ti,divider-clock†ªÖ‚páIOsys_clkout1@d70�ti,gate-clock†‚ pªdpll3_x2_ck�fixed-factor-clock†ødpll3_m2x2_ck�fixed-factor-clock†øIOdpll4_x2_ck�fixed-factor-clock†øcorex2_fck�fixed-factor-clock†øIOwkup_l4_ick�fixed-factor-clock†øIMOMcorex2_d3_fck�fixed-factor-clock†øI„O„corex2_d5_fck�fixed-factor-clock†øI…O…clockdomainscm@48004000 ti,omap3-cm‚H@@clocks+dummy_apb_pclk� fixed-clockÆomap_32k_fck� fixed-clockÆ€I?O?virt_12m_ck� fixed-clockÆ·IOvirt_13m_ck� fixed-clockÆÆ]@IOvirt_19200000_ck� fixed-clockÆ$øIOvirt_26000000_ck� fixed-clockÆŒº€IOvirt_38_4m_ck� fixed-clockÆIðIOdpll4_ck@d00�ti,omap3-dpll-per-clock†‚ D 0IOdpll4_m2_ck@d48�ti,divider-clock†Ö?‚ HáIOdpll4_m2x2_mul_ck�fixed-factor-clock†øI O dpll4_m2x2_ck@d00�ti,gate-clock† ª‚  I!O!omap_96m_alwon_fck�fixed-factor-clock†!øI(O(dpll3_ck@d00�ti,omap3-dpll-core-clock†‚ @ 0IOdpll3_m3_ck@1140�ti,divider-clock†ªÖ‚@áI"O"dpll3_m3x2_mul_ck�fixed-factor-clock†"øI#O#dpll3_m3x2_ck@d00�ti,gate-clock†#ª ‚  I$O$emu_core_alwon_ck�fixed-factor-clock†$øIaOasys_altclk� fixed-clockÆI-O-mcbsp_clks� fixed-clockÆIOdpll3_m2_ck@d40�ti,divider-clock†ªÖ‚ @áIOcore_ck�fixed-factor-clock†øI%O%dpll1_fck@940�ti,divider-clock†%ªÖ‚ @áI&O&dpll1_ck@904�ti,omap3-dpll-clock†&‚  $ @ 4IOdpll1_x2_ck�fixed-factor-clock†øI'O'dpll1_x2m2_ck@944�ti,divider-clock†'Ö‚ DáI;O;cm_96m_fck�fixed-factor-clock†(øI)O)omap_96m_fck@d40� ti,mux-clock†)ª‚ @IDODdpll4_m3_ck@e40�ti,divider-clock†ªÖ ‚@áI*O*dpll4_m3x2_mul_ck�fixed-factor-clock†*øI+O+dpll4_m3x2_ck@d00�ti,gate-clock†+ª‚  I,O,omap_54m_fck@d40� ti,mux-clock†,-ª‚ @I7O7cm_96m_d2_fck�fixed-factor-clock†)øI.O.omap_48m_fck@d40� ti,mux-clock†.-ª‚ @I/O/omap_12m_fck�fixed-factor-clock†/øIFOFdpll4_m4_ck@e40�ti,divider-clock†Ö ‚@áI0O0dpll4_m4x2_mul_ck�ti,fixed-factor-clock†0#1>I1O1dpll4_m4x2_ck@d00�ti,gate-clock†1ª‚  >IˆOˆdpll4_m5_ck@f40�ti,divider-clock†Ö?‚@áI2O2dpll4_m5x2_mul_ck�ti,fixed-factor-clock†2#1>I3O3dpll4_m5x2_ck@d00�ti,gate-clock†3ª‚  >IiOidpll4_m6_ck@1140�ti,divider-clock†ªÖ?‚@áI4O4dpll4_m6x2_mul_ck�fixed-factor-clock†4øI5O5dpll4_m6x2_ck@d00�ti,gate-clock†5ª‚  I6O6emu_per_alwon_ck�fixed-factor-clock†6øIbObclkout2_src_gate_ck@d70� ti,composite-no-wait-gate-clock†%ª‚ pI8O8clkout2_src_mux_ck@d70�ti,composite-mux-clock†%)7‚ pI9O9clkout2_src_ck�ti,composite-clock†89I:O:sys_clkout2@d70�ti,divider-clock†:ªÖ@‚ pQmpu_ck�fixed-factor-clock†;øI<O<arm_fck@924�ti,divider-clock†<‚ $Öemu_mpu_alwon_ck�fixed-factor-clock†<øIcOcl3_ick@a40�ti,divider-clock†%Ö‚ @áI=O=l4_ick@a40�ti,divider-clock†=ªÖ‚ @áI>O>rm_ick@c40�ti,divider-clock†>ªÖ‚ @ágpt10_gate_fck@a00�ti,composite-gate-clock†ª ‚ I@O@gpt10_mux_fck@a40�ti,composite-mux-clock†?ª‚ @IAOAgpt10_fck�ti,composite-clock†@Agpt11_gate_fck@a00�ti,composite-gate-clock†ª ‚ IBOBgpt11_mux_fck@a40�ti,composite-mux-clock†?ª‚ @ICOCgpt11_fck�ti,composite-clock†BCcore_96m_fck�fixed-factor-clock†DøIOmmchs2_fck@a00�ti,wait-gate-clock†‚ ªI³O³mmchs1_fck@a00�ti,wait-gate-clock†‚ ªI´O´i2c3_fck@a00�ti,wait-gate-clock†‚ ªIµOµi2c2_fck@a00�ti,wait-gate-clock†‚ ªI¶O¶i2c1_fck@a00�ti,wait-gate-clock†‚ ªI·O·mcbsp5_gate_fck@a00�ti,composite-gate-clock†ª ‚ IOmcbsp1_gate_fck@a00�ti,composite-gate-clock†ª ‚ IOcore_48m_fck�fixed-factor-clock†/øIEOEmcspi4_fck@a00�ti,wait-gate-clock†E‚ ªI¸O¸mcspi3_fck@a00�ti,wait-gate-clock†E‚ ªI¹O¹mcspi2_fck@a00�ti,wait-gate-clock†E‚ ªIºOºmcspi1_fck@a00�ti,wait-gate-clock†E‚ ªI»O»uart2_fck@a00�ti,wait-gate-clock†E‚ ªI¼O¼uart1_fck@a00�ti,wait-gate-clock†E‚ ª I½O½core_12m_fck�fixed-factor-clock†FøIGOGhdq_fck@a00�ti,wait-gate-clock†G‚ ªI¾O¾core_l3_ick�fixed-factor-clock†=øIHOHsdrc_ick@a10�ti,wait-gate-clock†H‚ ªI‰O‰gpmc_fck�fixed-factor-clock†Høcore_l4_ick�fixed-factor-clock†>øIIOImmchs2_ick@a10�ti,omap3-interface-clock†I‚ ªI¿O¿mmchs1_ick@a10�ti,omap3-interface-clock†I‚ ªIÀOÀhdq_ick@a10�ti,omap3-interface-clock†I‚ ªIÁOÁmcspi4_ick@a10�ti,omap3-interface-clock†I‚ ªIÂOÂmcspi3_ick@a10�ti,omap3-interface-clock†I‚ ªIÃOÃmcspi2_ick@a10�ti,omap3-interface-clock†I‚ ªIÄOÄmcspi1_ick@a10�ti,omap3-interface-clock†I‚ ªIÅOÅi2c3_ick@a10�ti,omap3-interface-clock†I‚ ªIÆOÆi2c2_ick@a10�ti,omap3-interface-clock†I‚ ªIÇOÇi2c1_ick@a10�ti,omap3-interface-clock†I‚ ªIÈOÈuart2_ick@a10�ti,omap3-interface-clock†I‚ ªIÉOÉuart1_ick@a10�ti,omap3-interface-clock†I‚ ª IÊOÊgpt11_ick@a10�ti,omap3-interface-clock†I‚ ª IËOËgpt10_ick@a10�ti,omap3-interface-clock†I‚ ª IÌOÌmcbsp5_ick@a10�ti,omap3-interface-clock†I‚ ª IÍOÍmcbsp1_ick@a10�ti,omap3-interface-clock†I‚ ª IÎOÎomapctrl_ick@a10�ti,omap3-interface-clock†I‚ ªIÏOÏdss_tv_fck@e00�ti,gate-clock†7‚ªI®O®dss_96m_fck@e00�ti,gate-clock†D‚ªI¯O¯dss2_alwon_fck@e00�ti,gate-clock†‚ªI°O°dummy_ck� fixed-clockÆgpt1_gate_fck@c00�ti,composite-gate-clock†ª‚ IJOJgpt1_mux_fck@c40�ti,composite-mux-clock†?‚ @IKOKgpt1_fck�ti,composite-clock†JKaes2_ick@a10�ti,omap3-interface-clock†Iª‚ IÐOÐwkup_32k_fck�fixed-factor-clock†?øILOLgpio1_dbck@c00�ti,gate-clock†L‚ ªI¥O¥sha12_ick@a10�ti,omap3-interface-clock†I‚ ªIÑOÑwdt2_fck@c00�ti,wait-gate-clock†L‚ ªI¦O¦wdt2_ick@c10�ti,omap3-interface-clock†M‚ ªI§O§wdt1_ick@c10�ti,omap3-interface-clock†M‚ ªI¨O¨gpio1_ick@c10�ti,omap3-interface-clock†M‚ ªI©O©omap_32ksync_ick@c10�ti,omap3-interface-clock†M‚ ªIªOªgpt12_ick@c10�ti,omap3-interface-clock†M‚ ªI«O«gpt1_ick@c10�ti,omap3-interface-clock†M‚ ªI¬O¬per_96m_fck�fixed-factor-clock†(øI O per_48m_fck�fixed-factor-clock†/øINONuart3_fck@1000�ti,wait-gate-clock†N‚ª I‹O‹gpt2_gate_fck@1000�ti,composite-gate-clock†ª‚IOOOgpt2_mux_fck@1040�ti,composite-mux-clock†?‚@IPOPgpt2_fck�ti,composite-clock†OPgpt3_gate_fck@1000�ti,composite-gate-clock†ª‚IQOQgpt3_mux_fck@1040�ti,composite-mux-clock†?ª‚@IRORgpt3_fck�ti,composite-clock†QRgpt4_gate_fck@1000�ti,composite-gate-clock†ª‚ISOSgpt4_mux_fck@1040�ti,composite-mux-clock†?ª‚@ITOTgpt4_fck�ti,composite-clock†STgpt5_gate_fck@1000�ti,composite-gate-clock†ª‚IUOUgpt5_mux_fck@1040�ti,composite-mux-clock†?ª‚@IVOVgpt5_fck�ti,composite-clock†UVgpt6_gate_fck@1000�ti,composite-gate-clock†ª‚IWOWgpt6_mux_fck@1040�ti,composite-mux-clock†?ª‚@IXOXgpt6_fck�ti,composite-clock†WXgpt7_gate_fck@1000�ti,composite-gate-clock†ª‚IYOYgpt7_mux_fck@1040�ti,composite-mux-clock†?ª‚@IZOZgpt7_fck�ti,composite-clock†YZgpt8_gate_fck@1000�ti,composite-gate-clock†ª ‚I[O[gpt8_mux_fck@1040�ti,composite-mux-clock†?ª‚@I\O\gpt8_fck�ti,composite-clock†[\gpt9_gate_fck@1000�ti,composite-gate-clock†ª ‚I]O]gpt9_mux_fck@1040�ti,composite-mux-clock†?ª‚@I^O^gpt9_fck�ti,composite-clock†]^per_32k_alwon_fck�fixed-factor-clock†?øI_O_gpio6_dbck@1000�ti,gate-clock†_‚ªIŒOŒgpio5_dbck@1000�ti,gate-clock†_‚ªI�O�gpio4_dbck@1000�ti,gate-clock†_‚ªIŽOŽgpio3_dbck@1000�ti,gate-clock†_‚ªI�O�gpio2_dbck@1000�ti,gate-clock†_‚ª I�O�wdt3_fck@1000�ti,wait-gate-clock†_‚ª I‘O‘per_l4_ick�fixed-factor-clock†>øI`O`gpio6_ick@1010�ti,omap3-interface-clock†`‚ªI’O’gpio5_ick@1010�ti,omap3-interface-clock†`‚ªI“O“gpio4_ick@1010�ti,omap3-interface-clock†`‚ªI”O”gpio3_ick@1010�ti,omap3-interface-clock†`‚ªI•O•gpio2_ick@1010�ti,omap3-interface-clock†`‚ª I–O–wdt3_ick@1010�ti,omap3-interface-clock†`‚ª I—O—uart3_ick@1010�ti,omap3-interface-clock†`‚ª I˜O˜uart4_ick@1010�ti,omap3-interface-clock†`‚ªI™O™gpt9_ick@1010�ti,omap3-interface-clock†`‚ª IšOšgpt8_ick@1010�ti,omap3-interface-clock†`‚ª I›O›gpt7_ick@1010�ti,omap3-interface-clock†`‚ªIœOœgpt6_ick@1010�ti,omap3-interface-clock†`‚ªI�O�gpt5_ick@1010�ti,omap3-interface-clock†`‚ªIžOžgpt4_ick@1010�ti,omap3-interface-clock†`‚ªIŸOŸgpt3_ick@1010�ti,omap3-interface-clock†`‚ªI O gpt2_ick@1010�ti,omap3-interface-clock†`‚ªI¡O¡mcbsp2_ick@1010�ti,omap3-interface-clock†`‚ªI¢O¢mcbsp3_ick@1010�ti,omap3-interface-clock†`‚ªI£O£mcbsp4_ick@1010�ti,omap3-interface-clock†`‚ªI¤O¤mcbsp2_gate_fck@1000�ti,composite-gate-clock†ª‚I O mcbsp3_gate_fck@1000�ti,composite-gate-clock†ª‚I O mcbsp4_gate_fck@1000�ti,composite-gate-clock†ª‚IOemu_src_mux_ck@1140� ti,mux-clock†abc‚@IdOdemu_src_ck�ti,clkdm-gate-clock†dIeOepclk_fck@1140�ti,divider-clock†eªÖ‚@ápclkx2_fck@1140�ti,divider-clock†eªÖ‚@áatclk_fck@1140�ti,divider-clock†eªÖ‚@átraceclk_src_fck@1140� ti,mux-clock†abcª‚@IfOftraceclk_fck@1140�ti,divider-clock†fª Ö‚@ásecure_32k_fck� fixed-clockÆ€IgOggpt12_fck�fixed-factor-clock†gøwdt1_fck�fixed-factor-clock†gøsecurity_l4_ick2�fixed-factor-clock†>øIhOhaes1_ick@a14�ti,omap3-interface-clock†hª‚ rng_ick@a14�ti,omap3-interface-clock†h‚ ªsha11_ick@a14�ti,omap3-interface-clock†h‚ ªdes1_ick@a14�ti,omap3-interface-clock†h‚ ªcam_mclk@f00�ti,gate-clock†iª‚>cam_ick@f10�!ti,omap3-no-wait-interface-clock†>‚ªIØOØcsi2_96m_fck@f00�ti,gate-clock†‚ªIÙOÙsecurity_l3_ick�fixed-factor-clock†=øIjOjpka_ick@a14�ti,omap3-interface-clock†j‚ ªicr_ick@a10�ti,omap3-interface-clock†I‚ ªdes2_ick@a10�ti,omap3-interface-clock†I‚ ªmspro_ick@a10�ti,omap3-interface-clock†I‚ ªmailboxes_ick@a10�ti,omap3-interface-clock†I‚ ªssi_l4_ick�fixed-factor-clock†>øIqOqsr1_fck@c00�ti,wait-gate-clock†‚ ªsr2_fck@c00�ti,wait-gate-clock†‚ ªsr_l4_ick�fixed-factor-clock†>ødpll2_fck@40�ti,divider-clock†%ªÖ‚@áIkOkdpll2_ck@4�ti,omap3-dpll-clock†k‚$@4gy�IlOldpll2_m2_ck@44�ti,divider-clock†lÖ‚DáImOmiva2_ck@0�ti,wait-gate-clock†m‚ªIÚOÚmodem_fck@a00�ti,omap3-interface-clock†‚ ªIÛOÛsad2d_ick@a10�ti,omap3-interface-clock†=‚ ªIÜOÜmad2d_ick@a18�ti,omap3-interface-clock†=‚ ªIÝOÝmspro_fck@a00�ti,wait-gate-clock†‚ ªssi_ssr_gate_fck_3430es2@a00� ti,composite-no-wait-gate-clock†ª‚ InOnssi_ssr_div_fck_3430es2@a40�ti,composite-divider-clock†ª‚ @$•IoOossi_ssr_fck_3430es2�ti,composite-clock†noIpOpssi_sst_fck_3430es2�fixed-factor-clock†pøIöOöhsotgusb_ick_3430es2@a10�"ti,omap3-hsotgusb-interface-clock†H‚ ªIŠOŠssi_ick_3430es2@a10�ti,omap3-ssi-interface-clock†q‚ ªI÷O÷usim_gate_fck@c00�ti,composite-gate-clock†Dª ‚ I|O|sys_d2_ck�fixed-factor-clock†øIsOsomap_96m_d2_fck�fixed-factor-clock†DøItOtomap_96m_d4_fck�fixed-factor-clock†DøIuOuomap_96m_d8_fck�fixed-factor-clock†DøIvOvomap_96m_d10_fck�fixed-factor-clock†Dø IwOwdpll5_m2_d4_ck�fixed-factor-clock†røIxOxdpll5_m2_d8_ck�fixed-factor-clock†røIyOydpll5_m2_d16_ck�fixed-factor-clock†røIzOzdpll5_m2_d20_ck�fixed-factor-clock†røI{O{usim_mux_fck@c40�ti,composite-mux-clock(†stuvwxyz{ª‚ @áI}O}usim_fck�ti,composite-clock†|}usim_ick@c10�ti,omap3-interface-clock†M‚ ª I­O­dpll5_ck@d04�ti,omap3-dpll-clock†‚  $ L 4gyI~O~dpll5_m2_ck@d50�ti,divider-clock†~Ö‚ PáIrOrsgx_gate_fck@b00�ti,composite-gate-clock†%ª‚ I†O†core_d3_ck�fixed-factor-clock†%øIOcore_d4_ck�fixed-factor-clock†%øI€O€core_d6_ck�fixed-factor-clock†%øI�O�omap_192m_alwon_fck�fixed-factor-clock†!øI‚O‚core_d2_ck�fixed-factor-clock†%øIƒOƒsgx_mux_fck@b40�ti,composite-mux-clock †€�)‚ƒ„…‚ @I‡O‡sgx_fck�ti,composite-clock††‡sgx_ick@b10�ti,wait-gate-clock†=‚ ªIÞOÞcpefuse_fck@a08�ti,gate-clock†‚ ªIÒOÒts_fck@a08�ti,gate-clock†?‚ ªIÓOÓusbtll_fck@a08�ti,wait-gate-clock†r‚ ªIÔOÔusbtll_ick@a18�ti,omap3-interface-clock†I‚ ªIÕOÕmmchs3_ick@a10�ti,omap3-interface-clock†I‚ ªIÖOÖmmchs3_fck@a00�ti,wait-gate-clock†‚ ªI×O×dss1_alwon_fck_3430es2@e00�ti,dss-gate-clock†ˆª‚>I±O±dss_ick_3430es2@e10�ti,omap3-dss-interface-clock†>‚ªI²O²usbhost_120m_fck@1400�ti,gate-clock†r‚ªIßOßusbhost_48m_fck@1400�ti,dss-gate-clock†/‚ªIàOàusbhost_ick@1410�ti,omap3-dss-interface-clock†>‚ªIáOáclockdomainscore_l3_clkdmti,clockdomain†‰Šdpll3_clkdmti,clockdomain†dpll1_clkdmti,clockdomain†per_clkdmti,clockdomainh†‹Œ�Ž��‘’“”•–—˜™š›œ�žŸ ¡¢£¤emu_clkdmti,clockdomain†edpll4_clkdmti,clockdomain†wkup_clkdmti,clockdomain$†¥¦§¨©ª«¬­dss_clkdmti,clockdomain†®¯°±²core_l4_clkdmti,clockdomain”†³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×cam_clkdmti,clockdomain†ØÙiva2_clkdmti,clockdomain†Údpll2_clkdmti,clockdomain†ld2d_clkdmti,clockdomain †ÛÜÝdpll5_clkdmti,clockdomain†~sgx_clkdmti,clockdomain†Þusbhost_clkdmti,clockdomain †ßàácounter@48320000ti,omap-counter32k‚H2  Ãcounter_32kinterrupt-controller@48200000ti,omap3-intcåÔ‚H IOdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdma‚H`¸ ¡¬ ¹`IOgpio@48310000ti,omap3-gpio‚H1¸Ãgpio1ÆØèåÔIðOðgpio@49050000ti,omap3-gpio‚I¸Ãgpio2ØèåÔgpio@49052000ti,omap3-gpio‚I ¸Ãgpio3ØèåÔgpio@49054000ti,omap3-gpio‚I@¸ Ãgpio4ØèåÔgpio@49056000ti,omap3-gpio‚I`¸!Ãgpio5ØèåÔgpio@49058000ti,omap3-gpio‚I€¸"Ãgpio6ØèåÔIùOùserial@4806a000ti,omap3-uart‚H  ôH·12¼txrxÃuart1ÆÜlserial@4806c000ti,omap3-uart‚HÀôI·34¼txrxÃuart2ÆÜlserial@49020000ti,omap3-uart‚IôJ·56¼txrxÃuart3ÆÜli2c@48070000 ti,omap3-i2c‚H€¸8·¼txrx+Ãi2c1Æ'¬@twl@48‚H¸ ti,twl4030åÔdefaultâãaudioti,twl4030-audiocodecrtcti,twl4030-rtc¸ bciti,twl4030-bci¸  äwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1m 'À… regulator-vdacti,twl4030-vdacmw@…w@IóOóregulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1m:�…0°IèOèregulator-vmmc2ti,twl4030-vmmc2m:�…0°regulator-vusb1v5ti,twl4030-vusb1v5IåOåregulator-vusb1v8ti,twl4030-vusb1v8IæOæregulator-vusb3v1ti,twl4030-vusb3v1IäOäregulator-vpll1ti,twl4030-vpll1 ^vdds_dsimw@…w@IòOòregulator-vpll2ti,twl4030-vpll2mw@…w@regulator-vsimti,twl4030-vsimmw@…-ÆÀIéOégpioti,twl4030-gpioØèåÔ.:¡ÆIúOútwl4030-usbti,twl4030-usb¸ GåUæcäqzpwmti,twl4030-pwm…pwmledti,twl4030-pwmled…pwrbuttonti,twl4030-pwrbutton¸keypadti,twl4030-keypad¸� D³?  @A Bsrmadcti,twl4030-madc¸Ài2c@48072000 ti,omap3-i2c‚H €¸9·¼txrx+Ãi2c2Æ€IþOþi2c@48060000 ti,omap3-i2c‚H€¸=·¼txrx+Ãi2c3 Òdisabledmailbox@48094000ti,omap3-mailboxÃmailbox‚H @¸Ùå÷dsp   spi@48098000ti,omap2-mcspi‚H €¸A+Ãmcspi1@·#$%&'()* ¼tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspi‚H  ¸B+Ãmcspi2 ·+,-.¼tx0rx0tx1rx1spi@480b8000ti,omap2-mcspi‚H €¸[+Ãmcspi3 ·¼tx0rx0tx1rx1spi@480ba000ti,omap2-mcspi‚H  ¸0+Ãmcspi4·FG¼tx0rx01w@480b2000 ti,omap3-1w‚H ¸:Ãhdq1wmmc@4809c000ti,omap3-hsmmc‚H À¸SÃmmc1-·=>¼txrx:çGèSécmmc@480b4000ti,omap3-hsmmc‚H @¸VÃmmc2·/0¼txrx Òdisabledmmc@480ad000ti,omap3-hsmmc‚H и^Ãmmc3·MN¼txrx Òdisabledmmu@480bd400mti,omap2-iommu‚H Ô€¸Ãmmu_ispzIøOømmu@5d000000mti,omap2-iommu‚]€¸Ãmmu_iva Òdisabledwdt@48314000 ti,omap3-wdt‚H1@€ Ãwd_timer2 Òdisabledmcbsp@48074000ti,omap3-mcbsp‚H@ÿŠmpu ¸;< ”commontxrx¤€Ãmcbsp1· ¼txrx†ê�fck Òdisabledmcbsp@49022000ti,omap3-mcbsp‚I ÿI€ÿ Šmpusidetone¸>?”commontxrxsidetone¤Ãmcbsp2mcbsp2_sidetone·!"¼txrx†ë¢�fckickÒokayIûOûmcbsp@49024000ti,omap3-mcbsp‚I@ÿI ÿ Šmpusidetone¸YZ”commontxrxsidetone¤€Ãmcbsp3mcbsp3_sidetone·¼txrx†ì£�fckick Òdisabledmcbsp@49026000ti,omap3-mcbsp‚I`ÿŠmpu ¸67 ”commontxrx¤€Ãmcbsp4·¼txrx†í�fck Òdisabledmcbsp@48096000ti,omap3-mcbsp‚H `ÿŠmpu ¸QR ”commontxrx¤€Ãmcbsp5·¼txrx†î�fck Òdisabledsham@480c3000ti,omap3-shamÃsham‚H 0d¸1·E¼rxsmartreflex@480cb000ti,omap3-smartreflex-coreÃsmartreflex_core‚H °¸smartreflex@480c9000ti,omap3-smartreflex-ivaÃsmartreflex_mpu_iva‚H �¸timer@48318000ti,omap3430-timer‚H1€¸%Ãtimer1³timer@49032000ti,omap3430-timer‚I ¸&Ãtimer2timer@49034000ti,omap3430-timer‚I@¸'Ãtimer3timer@49036000ti,omap3430-timer‚I`¸(Ãtimer4timer@49038000ti,omap3430-timer‚I€¸)Ãtimer5Âtimer@4903a000ti,omap3430-timer‚I ¸*Ãtimer6Âtimer@4903c000ti,omap3430-timer‚IÀ¸+Ãtimer7Âtimer@4903e000ti,omap3430-timer‚Ià¸,Ãtimer8ÏÂtimer@49040000ti,omap3430-timer‚I¸-Ãtimer9Ïtimer@48086000ti,omap3430-timer‚H`¸.Ãtimer10Ïtimer@48088000ti,omap3430-timer‚H€¸/Ãtimer11Ïtimer@48304000ti,omap3430-timer‚H0@¸_Ãtimer12³Üusbhstll@48062000 ti,usbhs-tll‚H ¸N Ãusb_tll_hsusbhshost@48064000ti,usbhs-host‚H@ Ãusb_host_hs+Íohci@48064400ti,ohci-omap3‚HD ¸Lehci@48064800 ti,ehci-omap‚HH ¸Mgpmc@6e000000ti,omap3430-gpmcÃgpmc‚nи·¼rxtxìø+åÔØèÍ,IïOïnand@0,0ti,omap2-nand ‚ ï¸ +sw;LZ,l,~�" ,³(Â6Ñ@àRñR(+x-loader@0 ,X-Loader‚bootloaders@80000,U-Boot‚bootloaders_env@260000 ,U-Boot Env‚&kernel@280000,Kernel‚(@filesystem@680000 ,File System‚h˜ethernet@0,0davicom,dm9000‚2 ð¸=Oao‰LZ´l´~� 0£6¨±6³¨àºñºÑ�¿ÙZðZ "usb_otg_hs@480ab000ti,omap3-musb‚H °¸\]”mcdma Ãusb_otg_hs9DL dss@48050000 ti,omap3-dss‚HÒok Ãdss_core†±�fck+ÍdefaultñUòeódispc@48050400ti,omap3-dispc‚H¸ Ãdss_dispc†±�fckencoder@4804fc00 ti,omap3-dsi‚HüHþ@Hÿ Šprotophypll¸ Òdisabled Ãdss_dsi1†±° �fcksys_clkencoder@48050800ti,omap3-rfbi‚H Òdisabled Ãdss_rfbi†±²�fckickencoder@48050c00ti,omap3-venc‚H Òok Ãdss_venc†®�fckuóportendpoint�ô‘IOportendpoint�õ�IüOüssi-controller@48058000 ti,omap3-ssiÃssiÒok‚H€H�Šsysgdd¸G”gdd_mpu+Í †pö÷ �ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-port‚H H¨Štxrx ¸CDssi-port@4805b000ti,omap3-ssi-port‚H°H¸Štxrx ¸EFpinmux@480025d8 ti,omap3-padconfpinctrl-single‚H%Ø$+Ôåúÿisp@480bc000 ti,omap3-isp‚H ÀüH Ø|¸¨øWl¯�ports+bandgap@48002524‚H%$ti,omap34xx-bandgap»memory@80000000vmemory‚€leds gpio-ledsheartbeat,devkit8000::led1 Ñù×on åheartbeatmmc,devkit8000::led2 Ñù×onånoneusr,devkit8000::led3 Ñù×onåusrpmu_stat,devkit8000::pmu_stat Ñúsoundti,omap-twl4030 ûdevkit8000ûI Ext SpkPREDRIVELExt SpkPREDRIVERMAINMICMain MicMain MicMic Bias 1gpio_keys gpio-keysuser,user Ñð)encoder0 ti,tfp410 7úports+port@0‚endpoint�üIõOõport@1‚endpoint�ýIÿOÿconnector0dvi-connector,dviGOþportendpoint�ÿIýOýconnector1svideo-connector,tvportendpoint�IôOô compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display1display2device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyti,use-ledsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsstatus#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-width#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthdavicom,no-eepromgpmc,mux-add-datagpmc,wait-pingpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsmultipointnum-epsram-bitsvdds_dsi-supplyvdda_dac-supplyvdda-supplyremote-endpointti,channelsdata-linesiommusti,phy-type#thermal-sensor-cellsgpiosdefault-statelinux,default-triggerti,modelti,mcbspti,audio-routinglinux,codewakeup-sourcepowerdown-gpiosdigitalddc-i2c-bus